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[EN] SRAM technology has traditionally been used to implement processor caches since it is the fastest existing RAM technology.However,one of the major drawbacks of this technology is its high energy consumption.To reduce this energy consumption mode
Externí odkaz:
http://hdl.handle.net/10251/58428
Combining RAM technologies for hard-error recovery in L1 data caches working at very-low power modes
Autor:
Lorente Garcés, Vicente Jesús, Valero Bresó, Alejandro, Sahuquillo Borrás, Julio, Petit Martí, Salvador Vicente, Canal, Ramón, López Rodríguez, Pedro Juan, Duato Marín, José Francisco
Publikováno v:
Scopus-Elsevier
UPCommons. Portal del coneixement obert de la UPC
Universitat Politècnica de Catalunya (UPC)
RiuNet. Repositorio Institucional de la Universitat Politécnica de Valéncia
instname
Recercat. Dipósit de la Recerca de Catalunya
UPCommons. Portal del coneixement obert de la UPC
Universitat Politècnica de Catalunya (UPC)
RiuNet. Repositorio Institucional de la Universitat Politécnica de Valéncia
instname
Recercat. Dipósit de la Recerca de Catalunya
Low-power modes in modern microprocessors rely on low frequencies and low voltages to reduce the energy budget. Nevertheless, manufacturing induced parameter variations can make SRAM cells unreliable producing hard errors at supply voltages below Vcc
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_dedup___::8c699462327b2f04a44cae3544105bfa
https://hdl.handle.net/10251/75168
https://hdl.handle.net/10251/75168