Zobrazeno 1 - 10
of 170
pro vyhledávání: '"Loop splitting"'
Publikováno v:
Journal of High Energy Physics
Journal of High Energy Physics, Vol 2021, Iss 8, Pp 1-72 (2021)
Journal of high energy physics 08(8), 040 (2021). doi:10.1007/JHEP08(2021)040
Journal of High Energy Physics, Vol 2021, Iss 8, Pp 1-72 (2021)
Journal of high energy physics 08(8), 040 (2021). doi:10.1007/JHEP08(2021)040
Journal of high energy physics 08(8), 040 (2021). doi:10.1007/JHEP08(2021)040
At small inter-parton distances, double parton distributions receive their dominant contribution from the splitting of a single parton. We compute this mechanism at ne
At small inter-parton distances, double parton distributions receive their dominant contribution from the splitting of a single parton. We compute this mechanism at ne
Conference
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Publikováno v:
SciPost physics 7(2), 017 (2019). doi:10.21468/SciPostPhys.7.2.017
SciPost Physics, Vol 7, Iss 2, p 017 (2019)
SciPost Physics, Vol 7, Iss 2, p 017 (2019)
SciPost physics 7(2), 017 (2019). doi:10.21468/SciPostPhys.7.2.017
Double parton distributions (DPDs) receive a short-distance contribution from a single parton splitting to yield the two observed partons. We investigate this mechanism at next-t
Double parton distributions (DPDs) receive a short-distance contribution from a single parton splitting to yield the two observed partons. We investigate this mechanism at next-t
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_dedup___::466573f216b5b1dbdc60bc9d947116df
Autor:
Sanyam Mehta, Pen-Chung Yew
Publikováno v:
ACM Transactions on Architecture and Code Optimization. 13:1-25
In the wake of the current trend of increasing the number of cores on a chip, compiler optimizations for improving the memory performance have assumed increased importance. Loop fusion is one such key optimization that can alleviate memory and bandwi
Publikováno v:
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems. 35:1092-1104
Nested loops represent a significant portion of application runtime in multimedia and DSP applications, an important domain of applications for coarse-grained reconfigurable architectures (CGRAs). While conventional approaches to mapping nested loops
Autor:
Marco Bonvini, Simone Marzani
Publikováno v:
JHEP
Journal of High Energy Physics, Vol 2018, Iss 6, Pp 1-38 (2018)
Journal of High Energy Physics
Journal of High Energy Physics, Vol 2018, Iss 6, Pp 1-38 (2018)
Journal of High Energy Physics
We consider the expansion of small-$x$ resummed DGLAP splitting functions at next-to-leading logarithmic (NLL) accuracy to four-loop order, namely next-to-next-to-next-to-leading order (N$^3$LO). From this, we extract the exact LL and NLL small-$x$ c
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_dedup___::b40228b9f9c2d786fb2d562e4f302d86
http://hdl.handle.net/11567/912381
http://hdl.handle.net/11567/912381
Autor:
Shen-Iuan Liu, Ting-Kuei Kuan
Publikováno v:
IEEE Transactions on Circuits and Systems I: Regular Papers. 62:1873-1882
This paper presents a loop gain optimization technique for integer- $N$ digital phase-locked loops with a time-to-digital converter. Due to noise filtering properties, a phase-locked loop has an optimal loop gain which gives rise to the best jitter p
Publikováno v:
ACSSC
52nd Annual Asilomar Conference on Signals, Systems, and Computers
52nd Annual Asilomar Conference on Signals, Systems, and Computers
As a key optimisation method in high-level synthesis (HLS), high-performance loop pipelining is enabled by the static scheduling algorithm. When there are non-trivial memory dependencies in the loop, current HLS tools have to apply conservative pipel
Autor:
Joshua Davies
These proceedings describe a computation of the large-$n_f$ terms contributing to the QCD splitting functions at the fourth order in the strong coupling constant $\alpha_s$. Using the FORCER package for the reduction of four-loop two-point Feynman in
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_dedup___::e2d6355d016f06115be25dabbc698fa3
http://arxiv.org/abs/1709.00368
http://arxiv.org/abs/1709.00368
Publikováno v:
Parallel and Distributed Processing Symposium (IPDPS), 2017
Parallel and Distributed Processing Symposium (IPDPS), 2017, May 2017, Orlando, United States. pp.778-787, ⟨10.1109/IPDPS.2017.34⟩
IPDPS
Parallel and Distributed Processing Symposium (IPDPS), 2017, May 2017, Orlando, United States. pp.778-787, ⟨10.1109/IPDPS.2017.34⟩
IPDPS
International audience; Loop collapsing is a well-known loop transformation which combines some loops that are perfectly nested into one single loop. It allows to take advantage of the whole amount of parallelism exhibited by the collapsed loops, and
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_dedup___::473f9db850a79d4b1ddc1218c469993c
https://hal.inria.fr/hal-01581081/file/paper.pdf
https://hal.inria.fr/hal-01581081/file/paper.pdf