Zobrazeno 1 - 10
of 37
pro vyhledávání: '"Liang-Choo Hsia"'
Publikováno v:
Materials Science Forum. 858:229-232
In this study, different parameters of 4H-SiC epitaxial growth were used to investigate the influence on surface pits density. It was found that the density of surface pits can be reduced significantly at lower C/Si ratio condition but doping uniform
Autor:
Yue Ying Ong, Zhong Chen, Juan Boon Tan, Leong Ching Wai, Kai Chong Chan, Soon Wee Ho, Dong Kyun Sohn, David Yeo, Xuefen Ong, Liang Choo Hsia, Y.K. Lim, Kripesh Vaidyanathan
Publikováno v:
Microelectronics Reliability. 49:150-162
A systematic underfill selection approach has been presented to characterize and identify suitable underfill encapsulants for large size flip chip ball grid array (FCBGA) packages. In the selection scheme, a total of six evaluation factors such as fr
Autor:
Wu Ping Liu, Liang Choo Hsia, Chun Hui Low, Juan Boon Tan, Hai Cong, Xin Zhang, Yelehanka Ramachandramurthy Pradeep, Perera Chandima
Publikováno v:
Journal of Vacuum Science & Technology A: Vacuum, Surfaces, and Films. 24:1404-1409
In SiOCH (C-doped SiO2) via etch application, high polymer deposition chemistry is needed for better selectivity to both photoresist and underlying barrier materials. To prevent etch stop, high ion energy plasma is required to achieve a good process
Autor:
C.M. Chua, S.H. Goh, J.C.H. Phang, Y.H. Chan, Hao Tan, Robin Chen, Zhihong Mai, F. Zheng, Liang-Choo Hsia, Jeffrey Lam, J.W. Ting
Publikováno v:
International Symposium for Testing and Failure Analysis.
Dynamic Laser Stimulation (DLS) fault isolation techniques involve using an Automated Test Equipment (ATE) to run the device under certain test patterns together and a scanning laser beam to localize sites sensitive to laser stimulation. Such techniq
Autor:
Bei Chao Zhang, Fan Zhang, A.Y. Du, Wuping Liu, Y.H. Zhao, D.K. Sohn, Juan Boon Tan, Liang Choo Hsia, Yeow Kheng Lim, H. Liu
Publikováno v:
2010 IEEE International Reliability Physics Symposium.
The bimodality of upstream electromigration (EM) failures in the dual damascene structure of 45nm Cu interconnection process with low-k material is investigated, and the improvement is demonstrated. Two major early failure modes with voids forming in
Publikováno v:
2009 16th IEEE International Symposium on the Physical and Failure Analysis of Integrated Circuits.
A novel industry methodology has been developed to analyze TDDB reliability failure on Cu/Low-k SiCOH interconnects. Initial breakdown point is at interface between capping layer and metal line. Inline process control needs to be tightened to improve
Autor:
Jeffrey Lam, L. Zhu, Y.W. Goh, R. He, S.L. Toh, Q.F. Wang, H. Tan, H.B. Lin, Liang-Choo Hsia, P.K. Tan, Zhihong Mai, E. Hendarto, Q. Deng
Publikováno v:
2009 16th IEEE International Symposium on the Physical and Failure Analysis of Integrated Circuits.
Ni diffusion in sub-100 nm devices can adversely affect electrical performance, and contribute greatly to yield loss. Despite the tremendous advantages of Ni salicide technology over Ti or Co, there are problems associated with the intrinsic properti
Autor:
Y. H. Wang, M. S. Zhou, W. Lu, Huang Liu, B. F. Lin, L. Z. Wu, C. S. Seet, W. P. Liu, S. L. Liew, J. Widodo, Liang-Choo Hsia, C.H. Low, Z. H. Wang
Publikováno v:
2009 IEEE International Interconnect Technology Conference.
This paper presents some major integration challenges in Ultra low-k (ULK) Back-End-Of-Line (BEOL) interconnects for 45nm and beyond. The discussions mainly address the challenges that arise from ultra violet (UV) curing that cause changes in the com
Autor:
Juan Boon Tan, Dong Kyun Sohn, Y.K. Lim, C.Q. Chen, Wuping Liu, Beichao Zhang, Liang-Choo Hsia, W. Y. Zhang, Fan Zhang
Publikováno v:
2009 IEEE International Reliability Physics Symposium.
The correlation of time-dependent dielectric breakdown (TDDB) reliability failure with scratches generated from chemical mechanical polishing (CMP) in 45nm backend-ofline (BEOL) process is investigated and established. The wafer map of early TDDB fai
Publikováno v:
2008 International Symposium on VLSI Technology, Systems and Applications (VLSI-TSA).
An overview of the semiconductor roadmap of interconnects process transition from 0.13mum to 45nm using current proven state- of-the-art manufacturing technology in relation to the integration of dielectric material progressing from fluorinated silic