Zobrazeno 1 - 10
of 151
pro vyhledávání: '"Leong, Philip H. W."'
Publikováno v:
ACM Transactions on Reconfigurable Technology and Systems(TRETS),16, 3, Article 42 (2023). Journal Track of The International Conference on Field Programmable Technology (FPT'22), Hong Kong SAR, China
Machine learning ensembles combine multiple base models to produce a more accurate output. They can be applied to a range of machine learning problems, including anomaly detection. In this paper, we investigate how to maximize the composability and s
Externí odkaz:
http://arxiv.org/abs/2406.05999
Publikováno v:
International Conference on Field-Programmable Logic and Applications (FPL2024) in Turin, Italy, from 2nd to 6th September 2024
FPGAs have distinct advantages as a technology for deploying deep neural networks (DNNs) at the edge. Lookup Table (LUT) based networks, where neurons are directly modeled using LUTs, help maximize this promise of offering ultra-low latency and high
Externí odkaz:
http://arxiv.org/abs/2406.04910
Autor:
Huang, Teng-Hui, Dahanayaka, Thilini, Thilakarathna, Kanchana, Leong, Philip H. W., Gamal, Hesham El
Wireless fingerprinting refers to a device identification method leveraging hardware imperfections and wireless channel variations as signatures. Beyond physical layer characteristics, recent studies demonstrated that user behaviors could be identifi
Externí odkaz:
http://arxiv.org/abs/2303.15860
While integer arithmetic has been widely adopted for improved performance in deep quantized neural network inference, training remains a task primarily executed using floating point arithmetic. This is because both high dynamic range and numerical ac
Externí odkaz:
http://arxiv.org/abs/2009.13108
Autor:
Rasoulinezhad, SeyedRamin, Siddhartha, Zhou, Hao, Wang, Lingli, Boland, David, Leong, Philip H. W.
We propose two tiers of modifications to FPGA logic cell architecture to deliver a variety of performance and utilization benefits with only minor area overheads. In the irst tier, we augment existing commercial logic cell datapaths with a 6-input XO
Externí odkaz:
http://arxiv.org/abs/2003.03043
Autor:
Rasoulinezhad, Seyedramin, Fox, Sean, Zhou, Hao, Wang, Lingli, Boland, David, Leong, Philip H. W.
Publikováno v:
International Conference on Field-Programmable Technology, {FPT} 2019,Tianjin, China, December 9-13, 2019
Binarized neural networks (BNNs) have shown exciting potential for utilising neural networks in embedded implementations where area, energy and latency constraints are paramount. With BNNs, multiply-accumulate (MAC) operations can be simplified to Xn
Externí odkaz:
http://arxiv.org/abs/2002.12900
Autor:
Faraone, Julian, Kumm, Martin, Hardieck, Martin, Zipf, Peter, Liu, Xueyuan, Boland, David, Leong, Philip H. W.
Low-precision arithmetic operations to accelerate deep-learning applications on field-programmable gate arrays (FPGAs) have been studied extensively, because they offer the potential to save silicon area or increase throughput. However, these benefit
Externí odkaz:
http://arxiv.org/abs/1911.08097
Autor:
Tridgell, Stephen, Kumm, Martin, Hardieck, Martin, Boland, David, Moss, Duncan, Zipf, Peter, Leong, Philip H. W.
The computational complexity of neural networks for large scale or real-time applications necessitates hardware acceleration. Most approaches assume that the network architecture and parameters are unknown at design time, permitting usage in a large
Externí odkaz:
http://arxiv.org/abs/1909.04509
Inference for state-of-the-art deep neural networks is computationally expensive, making them difficult to deploy on constrained hardware environments. An efficient way to reduce this complexity is to quantize the weight parameters and/or activations
Externí odkaz:
http://arxiv.org/abs/1807.00301
A low precision deep neural network training technique for producing sparse, ternary neural networks is presented. The technique incorporates hard- ware implementation costs during training to achieve significant model compression for inference. Trai
Externí odkaz:
http://arxiv.org/abs/1709.06262