Zobrazeno 1 - 8
of 8
pro vyhledávání: '"Leneesh Raghavan"'
Publikováno v:
IEEE Journal of Solid-State Circuits. 54:1852-1861
This paper presents a fast spinning-current Hall sensor with 568 ns overall delay for sub-microsecond overcurrent detection (OCD) in a magnetic current sensor. By combining the continuous-time chopping techniques and discrete-time dynamic offset canc
Publikováno v:
ESSCIRC
A spun Hall sensor with continuous-time chopping and ping-pong sampling techniques for fast overcurrent detection application is presented in this paper. The proposed background track-and-hold ping-pong comparator continuously tracks the input Hall s
Autor:
Manish Jain, C. Huang, Keisuke Saito, Wendemagegnehu T. Beyene, Kun-Yung Ken Chang, J. Wei, Deborah Dressier, T. J. Chin, Catherine Chen, Dave Secker, Phuong Le, Vijay Gadde, Chris Madden, Xingchao Yuan, Ting Wu, Chanh Tran, Mahabaleshwara, Sanku Mukherjee, Navin Kumar Mishra, Ling Yang, Leneesh Raghavan, Arul Sendhil, Amir Amirkhany, Hai Lan, Arun Vaidyanath, R. Schmitt, Gundlapalli Shanmukha Srinivas, Shuaeb Fazeel, Mohammad Hekmat, Kambiz Kaviani, Kapil Vyas, Jie Shen
Publikováno v:
IEEE Journal of Solid-State Circuits. 47:911-925
This paper presents a tri-modal asymmetric memory controller interface that achieves 12.8-Gbps single-ended (SE) signaling over 3" stripline FR4 traces. The controller can be configured to communicate with commercially available GDDR5 and DDR3 memori
Autor:
Ting Wu, Amir Amirkhany, Gundlapalli Shanmukha Srinivas, Norman Chan, J. Wei, Phuong Le, Mahabaleshwara, Kun-Yung Ken Chang, S. Fazeel, Wendemagegnehu T. Beyene, Chanh Tran, Keisuke Saito, K. Vyas, Vijay Gadde, Xudong Shi, Catherine Chen, Dave Secker, E. Ho, Mohammad Hekmat, Chris Madden, T. J. Chin, Navin Kumar Mishra, Manish Jain, Bing Ren Chuang, Chintan Thakkar, Arun Vaidyanath, R. Schmitt, Xingchao Yuan, Deborah Dressler, Jie Shen, S. Zhang, Chaofeng Huang, Kambiz Kaviani, Leneesh Raghavan
Publikováno v:
IEEE Journal of Solid-State Circuits. 47:926-937
This paper describes a tri-modal asymmetric bidirectional differential memory interface that supports data rates of up to 20 Gbps over 3" FR4 PCB channels while achieving power efficiency of 6.1 mW/Gbps at full speed. The interface also accommodates
Autor:
Ting Wu, Leneesh Raghavan
Publikováno v:
VLSI Design
To achieve high speed data signaling rates with the internal fast clock operating at half its speed,the XDR(extreme data rate) I/O link employs dual-edge signaling where in data bits are transmitted on both the edges(rise/fall) of transmit clock. Dut
Autor:
T. J. Chin, Hae-Chang Lee, Mahabaleshwara, Xudong Shi, Ken Chang, Jie Shen, Wendemagegnehu T. Beyene, Chris Madden, Alok Austin Gupta, Kashinath Prabhu, Norman Chan, Kambiz Kaviani, Catherine Chen, Ting Wu, Leneesh Raghavan
Publikováno v:
2009 IEEE Asian Solid-State Circuits Conference.
An 8Gb/s/link power optimized controller memory interface is implemented in TSMC 40nm G CMOS process. It is composed of 32 differential data links to support 32GB/s payload. The bimodal drivers of the request bus enable support of both 12 bits of 2Gb
Publikováno v:
ISVLSI
Low static phase offset is desired in Phase Locked Loops (PLL) employed in high speed I/O interfaces and frequency synthesizers. In this work, non idealities in phase frequency detector and charge pump contributing to static phase offset have been st
Autor:
Vijay Khawshe, Renu Rangnekar, Rajkumar Palwai, Kunal Desai, Abhijit M. Abhyankar, K. Vyas, Prateek Goyal, Leneesh Raghavan, Kashinath Prabhu, Pravin Kumar Venkatesan, Vijay Krishna, Thrivikraman M
Publikováno v:
VLSI Design
This paper focuses on the design of a 2.4Gbps to 4.8Gbps link developed in TSMC65nmG+ technology, for the high speed and high throughput interface between XDR™ (Extreme data rate) DRAM and ASIC. Applications such as HDTV and high end graphics requi