Zobrazeno 1 - 9
of 9
pro vyhledávání: '"Lekbir Cherif"'
Publikováno v:
Journal of Low Power Electronics and Applications, Vol 9, Iss 1, p 3 (2019)
Recently, the multi-bit flip-flop (MBFF) technique was introduced as a method for reducing the power consumption and chip area of integrated circuits (ICs) during the physical implementation stage of their development process. From the perspective of
Externí odkaz:
https://doaj.org/article/950aee6f2f5541d1b990d7b7575343b7
Publikováno v:
Journal of Engineering and Applied Sciences. 14:3243-3249
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::5a5affb3d27787f3bb659fc2601d6bbe
https://doi.org/10.36478/jeasci.2019.3243.3249
https://doi.org/10.36478/jeasci.2019.3243.3249
Publikováno v:
Journal of Engineering and Applied Sciences. 14:3283-3288
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::eba2138c8d8fb65030a0f4db24f113d9
https://doi.org/10.36478/jeasci.2019.3283.3288
https://doi.org/10.36478/jeasci.2019.3283.3288
Publikováno v:
Advances in Science, Technology and Engineering Systems Journal. 4:140-146
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::f6be36e997fdf13e930eb28eb57de555
https://doi.org/10.25046/aj040617
https://doi.org/10.25046/aj040617
Publikováno v:
Advances in Intelligent Systems and Computing ISBN: 9783030120641
Timing optimization techniques are widely used to meet the frequency and electrical design rules requirement of integrated circuits, they use logical and physical transformation to speed up the problematic signals and to close the design setup and ho
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::fc75928a21173feee398d62d9d7e49f3
https://doi.org/10.1007/978-3-030-12065-8_21
https://doi.org/10.1007/978-3-030-12065-8_21
Publikováno v:
CIST
Layer promotion is a new technique introduced recently for timing optimization at physical implementation stage of an Integrated Circuit (IC). In this paper, we will use the same idea to reduce the power consumption on the interconnection. We impleme
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::4850b3dc78e8bf5a638934e4e2bd95c0
https://doi.org/10.1109/cist.2018.8596605
https://doi.org/10.1109/cist.2018.8596605
Publikováno v:
Lecture Notes in Electrical Engineering ISBN: 9789811314049
The ever-increasing density of SoC (System on Chip) has made their power consumption an issue in their own right. We present a specific power reduction technique at physical design stage of the digital design SoC conception flow: Capacitance-Toggle r
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::62ad7ceb13379f2e1c850c6575db102c
https://doi.org/10.1007/978-981-13-1405-6_31
https://doi.org/10.1007/978-981-13-1405-6_31
Publikováno v:
Lecture Notes in Electrical Engineering ISBN: 9789811314049
The need for long life battery powered devices has grown drastically in the last decade, and the power consumption has become a factor of equal importance as speed in measuring a circuit performance. To satisfy the demand of such increasing market, m
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::aee7ba5400d629fc3ea1afc6ab78a45d
https://doi.org/10.1007/978-981-13-1405-6_35
https://doi.org/10.1007/978-981-13-1405-6_35
Publikováno v:
2018 4th International Conference on Optimization and Applications (ICOA).
The latest advancement in nanotechnology across a different range of industries, and the increased microelectronics market demand for high-performance, high complexity, and low power System on Chips (SoCs) have pushed the Electronic Design Automation
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::73f61f345e203c8ada6eb9ca24d2e1fe
https://doi.org/10.1109/icoa.2018.8370505
https://doi.org/10.1109/icoa.2018.8370505