Zobrazeno 1 - 10
of 21
pro vyhledávání: '"Lavanya Subramanian"'
Autor:
Behzad Boroujerdian, Ying Jing, Devashree Tripathy, Amit Kumar, Lavanya Subramanian, Luke Yen, Vincent Lee, Vivek Venkatesan, Amit Jindal, Robert Shearer, Vijay Janapa Reddi
Publikováno v:
ACM Transactions on Embedded Computing Systems. 22:1-35
Domain-specific SoCs (DSSoCs) are an attractive solution for domains with extremely stringent power, performance, and area constraints. However, DSSoCs suffer from two fundamental complexities. On the one hand, their many specialized hardware blocks
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::df56cec9d9fb9e5f8e48ddc9b550d2ef
https://doi.org/10.1145/3544016
https://doi.org/10.1145/3544016
Autor:
Onur Mutlu, Saugata Ghose, Anant Norion, Damla Senol Cali, Kalsi Gurpreet S, Can Firtina, Sreenivas Subramoneyon, Can Alkan, Mohammed Alser, Juan Gómez-Luna, Jeremie S. Kim, Amirali Boroumand, Rachata Ausavarungnirun, Zülal Bingöl, Allison Scibisz, Lavanya Subramanian
Publikováno v:
Proceedings of the Annual International Symposium on Microarchitecture, MICRO
MICRO
MICRO
Genome sequence analysis has enabled significant advancements in medical and scientific areas such as personalized medicine, outbreak tracing, and the understanding of evolution. Unfortunately, it is currently bottlenecked by the computational power
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_dedup___::ca03c6e72bce8f078290000d3bf77053
https://hdl.handle.net/11693/75751
https://hdl.handle.net/11693/75751
Autor:
Jason Mars, Lingjia Tang, Ram Srivatsa Kannan, Jeongseob Ahn, Lavanya Subramanian, Ashwin Raju
Publikováno v:
EuroSys
The microservice architecture has dramatically reduced user effort in adopting and maintaining servers by providing a catalog of functions as services that can be used as building blocks to construct applications. This has enabled datacenter operator
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::a99ff4e9d6a2cfccbda4f123f4f0e2da
https://doi.org/10.1145/3302424.3303958
https://doi.org/10.1145/3302424.3303958
Publikováno v:
IEEE Transactions on Parallel and Distributed Systems. 27:3071-3087
In a multicore system, applications running on different cores interfere at main memory. This inter-application interference degrades overall system performance and unfairly slows down applications. Prior works have developed application-aware memory
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::df3c222de036bb5877cb2c4f4507598e
https://doi.org/10.1109/tpds.2016.2526003
https://doi.org/10.1109/tpds.2016.2526003
Publikováno v:
International Journal of Information and Communication Technology Education. 12:62-75
Social Networking Sites (SNSs) are web-based facilities that allow for social interaction, sharing, communication and collaboration in today's world. In the current study, patterns of use of social media among students at a public Midwestern universi
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::6b03738607dc952a6e9ea03ce88f1e8a
https://doi.org/10.4018/ijicte.2016100106
https://doi.org/10.4018/ijicte.2016100106
Publikováno v:
ACM Transactions on Architecture and Code Optimization. 12:1-28
Modern SoCs integrate multiple CPU cores and hardware accelerators (HWAs) that share the same main memory system, causing interference among memory requests from different agents. The result of this interference, if it is not controlled well, is miss
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::85a4416f49a61ad1dfa42f9d454bd5bc
https://doi.org/10.1145/2847255
https://doi.org/10.1145/2847255
Publikováno v:
MEMSYS
Memory latency is a critical bottleneck in today's systems. The organization of the DRAM main memory necessitates sensing and reading an entire row (around 4KB) of data in order to access a single cache block. The benefit of this organization is that
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::784c2760fdde33b7544cd0a05a09790a
https://doi.org/10.1145/3240302.3240314
https://doi.org/10.1145/3240302.3240314
Autor:
Sreenivas Subramoney, Hong Wang, Lavanya Subramanian, Tanay Karnik, Kaushik Vaidyanathan, Anant V. Nori
Publikováno v:
DAC
DRAM memory access is a critical performance bottleneck. To access one cache block, an entire row needs to be sensed and amplified, data restored into the bitcells and the bitlines precharged, incurring high latency. Isolating the bitlines and sense
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_dedup___::d1ef0933c67a12f72cc38ad27b9e7026
https://doi.org/10.1145/3195970.3196008
https://doi.org/10.1145/3195970.3196008
The memory system is a fundamental performance and energy bottleneck in almost all computing systems. Recent system design, application, and technology trends that require more capacity, bandwidth, efficiency, and predictability out of the memory sys
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_dedup___::703183bb66eb63bfdf2f6cd102e497a1
Publikováno v:
VEE
Virtualization technologies has been widely adopted by large-scale cloud computing platforms. These virtualized systems employ distributed resource management (DRM) to achieve high resource utilization and energy savings by dynamically migrating and
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_dedup___::95fa028ecb34371b272e92cbef49f230
https://doi.org/10.1145/2817817.2731202
https://doi.org/10.1145/2817817.2731202