Zobrazeno 1 - 10
of 14
pro vyhledávání: '"Laurent Vandroux"'
Autor:
Vincent Mevellec, Dominique Suhr, Thierry Mourier, C Ribière, Frédéric Gaillard, Laurianne Religieux, Laurent Vandroux, Frédéric Raynal
Publikováno v:
ECS Transactions. 64:9-22
Nowadays, Through Silicon Vias (TSV) with High Aspect Ratio (HAR > 8:1) are seriously mandatory in the 3D Integrated Circuits in order to maintain semiconductor performance trends into new technological advances. Consequently, successful integration
Autor:
Caroline Rauer, Anne-Marie Charvet, Tina McCormick, Ionut Radu, Laurent Vandroux, Hubert Moriceau, Frank Fournel, Névine Rochat, Christophe Morales, François Rieutord
Publikováno v:
ECS Transactions. 50:287-295
Direct bonding is used to join two mirror-polished wafers without any additional material. This technique appears to be more and more used for microelectronics or microtechnologies applications such as 3D and optical integration, MEMS or heterostruct
Autor:
Caroline Rauer, Christophe Morales, Ionut Radu, Anne-Marie Charvet, François Rieutord, Frank Fournel, Tina McCormick, Laurent Vandroux, Hubert Moriceau, Névine Rochat
Publikováno v:
ECS Journal of Solid State Science and Technology. 2:Q147-Q150
Direct bonding is used to join two mirror-polished wafers without any additional material. This technique appears to be more and more used for microelectronics or microtechnologies applications such as 3D and optical integration, MEMS or heterostruct
Autor:
Steve Burgess, Chris Jones, Laurent Vandroux, Stephane Minoret, Thierry Mourier, Sylvain Maitrejean, Larissa Djomeni, Andrew Price, Sabrina Fadloun, A. Roule
Publikováno v:
Additional Conferences (Device Packaging, HiTEC, HiTEN, and CICMT). 2013:001322-001342
In recent years, 3D integration has become an alternative solution to the “More Moore” concept for providing circuits with higher performance or increased functionality. Via-Middle TSV is considered a reference integration scheme and requires voi
Autor:
F. Fillot, D. Muyard, M. Veillerot, A. Roule, Sylvain Maitrejean, Patrice Gergaud, S. Loubriat, Marc Verdier, Laurent Vandroux, Jean-Paul Barnes
Publikováno v:
Microelectronic Engineering
Microelectronic Engineering, Elsevier, 2011, 88 (5), pp.817-821
Microelectronic Engineering, 2011, 88 (5), pp.817-821
Microelectronic Engineering, Elsevier, 2011, 88 (5), pp.817-821
Microelectronic Engineering, 2011, 88 (5), pp.817-821
Phase change memories use a specific phase change material (PCMat) as a resistor element for information storage. To obtain good reliability and performances of the device, interface between PCMat and electrodes needs to be optimized. In this work, w
Autor:
Vincent Delaye, Laurent Vandroux, Etienne Grouiller, Jean Francois Lugand, Lea Di Cioccio, Maurice Rivoire, Pierric Gueguen, Laurent Clavelier
Publikováno v:
2010 Proceedings 60th Electronic Components and Technology Conference (ECTC).
Localized metal bonding is one of the main drivers for 3D technology implementation as it allows high vertical interconnection densities between piled up dies. In this paper we will present the direct bonding of tungsten blanket. The copper and tungs
Autor:
Alexis Farcy, R. Hida, Paul-Henri Haumesser, N. Sillon, E. Saugier, Jean Charbonnier, M. Neyret, David Henry, R. Anciant, G. Garnier, S. Cheramy, C. Brunet-Manquat, Maxime Rousseau, G. Druais, O. Hajji, Laurent Vandroux, J. Cuzzocrea, P. Chausse
Publikováno v:
2010 Proceedings 60th Electronic Components and Technology Conference (ECTC).
As 3D packaging technologies are becoming more and more present in packaging roadmap, applications with higher requirement are rising continuously. Today, one of the main applications requiring 3D technologies is dedicated to nomadic components, incl
Autor:
Laurent Clavelier, Lea Di Cioccio, Myriam Assous, Jerome Dechamp, Thomas Signamarcheix, Patrick Leduc, Rachid Taibi, Laurent Vandroux, Laurent Bally, Marc Zussy, Sophie Verrun, Francois de Crecy, Laurent-Luc Chapelon, D. Bouchu, Pierric Gueguen
Publikováno v:
3DIC
An innovative die to wafer stacking is proposed for 3D devices. Known good dices are bonded on a processed wafer thanks to direct bonding. Oxide layers or patterned oxide/copper layers are used as the bonding medium. After a first thinning, a low str
Autor:
Laurent Clavelier, R. Quenouillere, Maxime Rousseau, L. Di Cioccio, Nicolas Sillon, Myriam Assous, P. Gueguen, O. Rozeau, A. Roule, Alain Toffoli, P. Leduc, Antonio Roman, Laurent Vandroux, Barbara Charlet, Paul-Henri Haumesser, D. Bouchu, P. Sixt, Sylvain Maitrejean, M. Heitzmann, J.-P. Nieto, M. Zussy
Publikováno v:
2008 International Symposium on VLSI Technology, Systems and Applications (VLSI-TSA).
This paper presents several key technologies developed for high density 3D integration by circuit stacking, i.e. with an inter-strata connection pitch lower than 10 mum. Direct bonding technology, die-to-wafer self-assembly, wafer thinning process an
Autor:
Patrick Leduc, Nicolas Sillon, M. Assous, Lea DiCioccio, Michel Heitzmann, Paul-Henri Haumesser, Emmanuel Deronzier, Lucile Mage, D. Bouchu, Marc Zussy, Barbara Charlet, Anne Roule, Antonio Roman, Laurent Vandroux
Publikováno v:
Materials Research Society Symposium Proceedings.
This paper describes the process of copper through-Si via (TSV), 3 μm large and 15 μm deep, developed for tri-dimensional integrated circuits (3D 1C). The static resistance of this TSV was measured using a Kelvin structure and is 120±25 mΩ. A yie