Zobrazeno 1 - 10
of 37
pro vyhledávání: '"Laura Tosoratto"'
Autor:
Piero Vicini, Michele Martinelli, Davide Rossetti, Andrea Biagioni, Pierluigi Paolucci, F. Lo Cicero, Elena Pastorelli, Roberto Ammendola, Ottorino Frezza, Alessandro Lonardo, Laura Tosoratto, Francesco Simula
The APEnet+ board delivers a point-to-point, low-latency, 3D torus network interface card. In this paper we describe the latest generation of APEnet NIC, APEnet v5, integrated in a PCIe Gen3 board based on a state-of-the-art, 28 nm Altera Stratix V F
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_dedup___::ed202ed84b950bfcce62efa1bca5411a
http://arxiv.org/abs/2201.01088
http://arxiv.org/abs/2201.01088
Autor:
Robert Lajos Buecs, Devendra Rai, Lothar Thiele, Nicolas Fournel, Francesca Lo Cicero, Elena Pastorelli, Ottorino Frezza, Piero Vicini, Alessandro Lonardo, Clément Deschamps, Pierluigi Paolucci, Laura Tosoratto, Michele Martinelli, Luis Gabriel Murillo, Davide Rossetti, Ashraf El-Antably, Andrea Biagioni, Lars Schor, Frédéric Rousseau, Iuliana Bacivarov, Jan Henrik Weinstock, Rainer Leupers, Roberto Ammendola, Francesco Simula
Publikováno v:
Journal of Systems Architecture
Journal of Systems Architecture, Elsevier, 2015, Available online (In Press, Corrected Proof), ⟨10.1016/j.sysarc.2015.11.008⟩
Journal of Systems Architecture, Elsevier, 2015, Available online (In Press, Corrected Proof), ⟨10.1016/j.sysarc.2015.11.008⟩
International audience; In the next decade, a growing number of scientific and industrial applications will require power-efficient systems providing unprecedented computation, memory, and communication resources. A promising paradigm foresees the us
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_dedup___::1a05c41b084d3778c49555c930a42a25
https://doi.org/10.1016/j.sysarc.2015.11.008
https://doi.org/10.1016/j.sysarc.2015.11.008
Autor:
Francesca Lo Cicero, Alessandro Lonardo, Pierluigi Paolucci, Laura Tosoratto, Francesco Simula, Andrea Biagioni, Roberto Ammendola, Gert Goossens, Davide Rossetti, Piero Vicini, Ottorino Frezza, Werner Geurts
Publikováno v:
Future Generation Computer Systems. 53:109-118
We developed a point-to-point, low latency, 3D torus Network Controller integrated in an FPGA-based PCIe board which implements a Remote Direct Memory Access (RDMA) communication protocol. RDMA requires ability to directly access the remote node appl
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::91ab56c1f0aafe71835f9902cac4d759
https://doi.org/10.1016/j.future.2014.12.012
https://doi.org/10.1016/j.future.2014.12.012
Autor:
Alessandro Lonardo, Andrea Biagioni, Laura Tosoratto, Francesco Simula, Pierluigi Paolucci, Francesca Lo Cicero, Ottorino Frezza, Piero Vicini, Roberto Ammendola, Davide Rossetti
Publikováno v:
Future Generation Computer Systems. 53:90-99
Systemic fault tolerance is usually pursued with a number of strategies, like redundancy and checkpoint/restart; any of them needs to be triggered by safe and fast fault detection. We devised a hardware/software approach to fault detection that enabl
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::95310609b721b84f483d8bbf9730b05a
https://doi.org/10.1016/j.future.2014.12.015
https://doi.org/10.1016/j.future.2014.12.015
Autor:
Christoph Schumacher, Laura Tosoratto, Gerd Ascheid, Andreas Hoffmann, Dietmar Petras, Alessandro Lonardo, Jan Henrik Weinstock, Rainer Leupers
Publikováno v:
ACM Transactions on Embedded Computing Systems. 13:1-24
Architects and developers use virtual prototypes of computer systems to receive early feedback on hardware design decisions as well as to develop and debug system software. This is facilitated by the comprehensive inspection capabilities virtual prot
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::2c836f445db708ead78efd421e020b68
https://doi.org/10.1145/2678018
https://doi.org/10.1145/2678018
Publikováno v:
ISSE
In the satellite integration and verification process, test engineers tend to use a set of traditional methods like synoptics and direct telemetry inspection to assess significant measurements of the Equipment Under Test. The definition and implement
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::538c8a7b1c601afbf643e443b9d41292
https://doi.org/10.1109/syseng.2016.7753136
https://doi.org/10.1109/syseng.2016.7753136
Autor:
Pierluigi Paolucci, Luca Pontisso, Andrea Biagioni, Alessandro Lonardo, Roberto Piandani, Francesco Simula, M. Sozzi, Laura Tosoratto, Davide Rossetti, Massimiliano Fiorini, Ilaria Neri, Michele Martinelli, Roberto Ammendola, Piero Vicini, F. Lo Cicero, G. Lamanna, Ottorino Frezza, Elena Pastorelli
A GPU-based low level (L0) trigger is currently integrated in the experimental setup of the RICH detector of the NA62 experiment to assess the feasibility of building more refined physics-related trigger primitives and thus improve the trigger discri
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_dedup___::982936ece775de7b7753f6a5adb29779
http://hdl.handle.net/11568/860920
http://hdl.handle.net/11568/860920
Autor:
Claudio Santoni, A. Gianoli, Andrea Biagioni, Elena Pastorelli, Roberto Ammendola, A. Cotta Ramusino, Francesco Simula, Mauro Piccini, Pierluigi Paolucci, Ottorino Frezza, G. Lamanna, S. Chiozzi, Piero Vicini, Alessandro Lonardo, Roberto Piandani, Laura Tosoratto, Luca Pontisso, R. Fantechi, F. Lo Cicero, M. Sozzi, Massimiliano Fiorini, Ilaria Neri, M. Martinelli, Davide Rossetti
Publikováno v:
2015 IEEE Nuclear Science Symposium and Medical Imaging Conference (NSS/MIC).
A commercial Graphics Processing Unit (GPU) is used to build a fast Level 0 (L0) trigger system for the NA62 experiment at CERN. In particular, the parallel computing power of the GPU is exploited to perform real-time fitting in the Ring Imaging CHer
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_dedup___::e4637242aba6139d86eb90c3d1e31b9b
https://doi.org/10.1109/nssmic.2015.7581774
https://doi.org/10.1109/nssmic.2015.7581774
Autor:
M. Martinelli, Davide Rossetti, Ottorino Frezza, Alessandro Lonardo, M. Sozzi, Francesco Simula, Laura Tosoratto, G. Lamanna, Piero Vicini, Luca Pontisso, Andrea Biagioni, F. Lo Cicero, Pierluigi Paolucci, Elena Pastorelli, Roberto Ammendola
NaNet is a modular design of a family of FPGA-based PCIe Network Interface Cards specialized for low-latency real-time operations. NaNet features a Network Interface module that implements RDMA-style communications both with the host (CPU) and the GP
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_dedup___::ae692c53c86e0426b90cb7825ba621ab
http://hdl.handle.net/11568/860561
http://hdl.handle.net/11568/860561
Autor:
Roberto Ammendola, Alessandro Lonardo, Andrea Biagioni, Laura Tosoratto, Pierluigi Paolucci, Davide Rossetti, Francesca Lo Cicero, Piero Vicini, Ottorino Frezza, Francesco Simula
Publikováno v:
SRDS
QUonG is a parallel computing platform developed at INFN and equipped with commodity multi-core CPUs coupled with last generation NVIDIA GPUs. Computing nodes communicate through a point-to-point, high performance, low latency 3D torus network implem
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::49e064b350c0cde0badbb625c148b2b3
https://doi.org/10.1109/srds.2014.33
https://doi.org/10.1109/srds.2014.33