Zobrazeno 1 - 10
of 24
pro vyhledávání: '"Larry Clevenger"'
Publikováno v:
IEEE Transactions on Electron Devices. 69:7135-7140
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::4812084cd2938cfdf9b5206b492852fa
https://doi.org/10.1109/ted.2022.3216975
https://doi.org/10.1109/ted.2022.3216975
Publikováno v:
2018 IEEE International Interconnect Technology Conference (IITC).
The impact of back-end-of-line (BEOL) loading on logic performance at the 7nm, 5nm and 3nm technology nodes is evaluated using a combination of ab initio, finite-element and circuit analysis methods. The effects of processing variations, including li
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::10e9f0272e724de6b7b8ab9df376f328
https://doi.org/10.1109/iitc.2018.8430294
https://doi.org/10.1109/iitc.2018.8430294
Autor:
Nicholas Lanzillo, Karthik Yogendra, Chih-Chao Yang, Reinaldo Vega, Ron Bolam, Kisik Choi, Russ Robison, Larry Clevenger
Publikováno v:
ECS Meeting Abstracts. :1048-1048
Cobalt metallization in the back-end-of-line (BEOL) presents several interesting opportunities and challenges1-5. In this work, we evaluate the performance of Co interconnects at narrow BEOL pitch using chemical vapor deposition (CVD) for Co and a Ta
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::11bda4b766fb2c5d181c6f8f7a73ff65
https://doi.org/10.1149/ma2019-01/18/1048
https://doi.org/10.1149/ma2019-01/18/1048
Publikováno v:
2016 IEEE International Interconnect Technology Conference / Advanced Metallization Conference (IITC/AMC).
Quick calculation of capacitance without field solver simulations is desirable to evaluate process assumptions and predict interconnect performance with minimal computation time. At sub-10 nm technology nodes complex interconnect stacks and shrinking
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::d17a3e6a94fb9f63500088ae43ba43f4
https://doi.org/10.1109/iitc-amc.2016.7507711
https://doi.org/10.1109/iitc-amc.2016.7507711
Autor:
Larry Clevenger
Publikováno v:
2016 IEEE International Interconnect Technology Conference / Advanced Metallization Conference (IITC/AMC).
For a semiconductor technology node, the BEOL definition must support minimal parasitic impact to technology, sufficient reliability, required dimensional scaling from previous nodes for standard cell and custom logic requirements, and high yielding/
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::ade326cdd871a1e5f6ad5b5ef86a9522
https://doi.org/10.1109/iitc-amc.2016.7507640
https://doi.org/10.1109/iitc-amc.2016.7507640
Publikováno v:
SPIE Proceedings.
Design rules are created considering a wafer fail mechanism with the relevant design levels under various design cases, and the values are set to cover the worst scenario. Because of the simplification and generalization, design rule hinders, rather
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::2174a808ee48905f5dc9fe2859da5cc5
https://doi.org/10.1117/12.2218636
https://doi.org/10.1117/12.2218636
Publikováno v:
2015 IEEE International Interconnect Technology Conference and 2015 IEEE Materials for Advanced Metallization Conference (IITC/MAM).
Matched circuit components are widely used in logic circuits including resistors, capacitors and transistors. Any variations in those components could cause mismatch in circuit performance. In advanced technology nodes, double patterning (litho/etch/
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::9392c1d3a8a05287fb734f085a8c5aa4
https://doi.org/10.1109/iitc-mam.2015.7325648
https://doi.org/10.1109/iitc-mam.2015.7325648
Autor:
Scott Halle, Marcy Beard, Chiew-seng Koay, Oscar van der Straten, T. Levin, Lars Liemann, Juntao Li, D. Horak, Bryan Morris, Terry A. Spooner, S. Choi, Carol Boye, Donald F. Canaperi, Sylvie Mignot, Muthumanickam Sankarapandian, Elbert E. Huang, Chiahsun Tseng, James Hsueh-Chung Chen, Erin Mclellan, James J. Kelly, S. Fan, James J. Demarest, Nicole Saulnier, Hosadurga Shobha, Matthew E. Colburn, Balasubramanian S. Haran, Yongan Xu, Yunpeng Yin, Larry Clevenger, Christopher J. Waskiewicz, Mignot Yann, John C. Arnold
Publikováno v:
2012 IEEE International Interconnect Technology Conference.
This work demonstrates the building of a 56 nm pitch copper dual damascene interconnects which connects to the local interconnect level. This M1/V0 dual-damascene used a triple pitch split bi-directional M1 and a double pitch split contact (V0) schem
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::f371baddebc7d64eac10bf2c213e8ee5
https://doi.org/10.1109/iitc.2012.6251637
https://doi.org/10.1109/iitc.2012.6251637
Autor:
Eva E. Simonyi, William F. Landers, T. H. Ivers, Thomas M. Shaw, K. Ida, D. Jung, Sujatha Sankaran, Kaushal Patel, Johnny Widodo, Naftali E. Lustig, M. Chae, Kaushik Chanda, G. A. Biery, Wan-jae Park, J. Sucharitaves, W. Liu, T. Ko, Christos D. Dimitrakopoulos, M. Kelling, Stephen M. Gates, R. G. Filippi, D. Nielsen, John A. Fitzsimmons, O. Bravo, M. Beck, Satya V. Nitta, Terry A. Spooner, L. Economikos, T. Bolom, Alfred Grill, John G. Pellerin, X. Liu, Eric G. Liniger, G. Matusiewicz, E. Kaltalioglu, C. Tian, Mukta G. Farooq, F. Chen, David L. Rath, Griselda Bonilla, D. Nguyen, Nicholas C. M. Fuller, P. Davis, S. Arai, Daniel C. Edelstein, J.P. Doyle, Kevin S. Petrarca, P. Ong, Kaushik A. Kumar, H. Wendt, L. Wiggins, V. Patel, Stephan Grunow, W. Li, L. Nicholson, I. Melville, Sanjay Mehta, Stephen E. Greco, J. Werking, Robert L. Wisnieff, B. Moon, Darryl D. Restaino, S. Marokkey, R. Hannon, Myoung-Bum Lee, Theodorus E. Standaert, Shom Ponoth, Paul S. McLaughlin, R. Augur, P. V. McLaughlin, C. Labelle, A. Cowley, H. Shoba, S. Rhee, K. Malone, Stephan A. Cohen, Michael Lane, E.T. Ryan, H. Landis, Larry Clevenger, James R. Lloyd, James J. Demarest, Andrew H. Simon, K. Miyata
Publikováno v:
2006 International Electron Devices Meeting.
A high performance 45nm BEOL technology with proven reliability is presented. This BEOL has a hierarchical architecture with up to 10 wiring levels with 5 in PECVD SiCOH (k=3.0), and 3 in a newly-developed advanced PECVD ultralow-k (ULK) porous SiCOH
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::78f866f42f2dc1939f7fea86854709e4
https://doi.org/10.1109/iedm.2006.346782
https://doi.org/10.1109/iedm.2006.346782
Autor:
E. Duchesne, T. Ivers, C.-C. Yang, Clare Johanna Mccarthy, D. Hawken, Charles R. Davis, Timothy H. Daubenspeck, M. Cullinan, Larry Clevenger, J. Wright, T. Aoki, James J. Demarest, C. Das, Jon A. Casey, T. Shaw, Michael Lane, Daniel C. Edelstein, J. Nadeau-Filteau, Thomas E. Lombardi, A. Cowley, William F. Landers, David L. Questad, F. Beaulieu, X.-H. Liu, Wolfgang Sauter, Christopher D. Muzzy, Luc Guerin
Publikováno v:
Proceedings of the IEEE 2004 International Interconnect Technology Conference (IEEE Cat. No.04TH8729).
A summary of chip-to-package interaction (CPI) evaluations for a 90 nm PECVD low k technology will be discussed. This review will cover a 90 nm technology that uses Cu dual damascene interconnections with a SiCOH (K /spl sim/ 3.0) CVD BEOL insulator
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::6f471dd0cf5b4dde286b7a7fc3e854f0
https://doi.org/10.1109/iitc.2004.1345706
https://doi.org/10.1109/iitc.2004.1345706