Zobrazeno 1 - 10
of 18
pro vyhledávání: '"Larg Weiland"'
Autor:
Tomasz Brożek, Alberto Piadena, Larg Weiland, Michele Quarantelli, Alberto Coccoli, Sharad Saxena, Christopher Hess, Andrzej Strójwąs
Publikováno v:
2023 IEEE International Reliability Physics Symposium (IRPS).
Autor:
Sharad Saxena, Christopher Hess, Michele Quarantelli, Alberto Piadena, Larg Weiland, Rakesh Vallishayee, Yuan Yu, Dennis Ciplickas, Tomasz Brozek, Andrzej Strojwas
Publikováno v:
2022 IEEE 72nd Electronic Components and Technology Conference (ECTC).
Autor:
Stephen Lam, Christopher Hess, Larg Weiland, Matthew Moe, Xumin William Shen, John Chen, Indranil De, Marcin Strojwas, Tomasz Brozek
Publikováno v:
2022 IEEE 34th International Conference on Microelectronic Test Structures (ICMTS).
Evaluation of Truly Passive Crossbar Memory Arrays on Short Flow Characterization Vehicle Test Chips
Autor:
Christoph Dolainsky, Dennis Ciplickas, Tomasz Brozek, Rakesh Vallishayee, Christopher Hess, Khim Hong Ng, Hendrik Schneider, Meindert Lunenborg, Larg Weiland, Yuan Yu
Publikováno v:
2019 IEEE 32nd International Conference on Microelectronic Test Structures (ICMTS).
More and more non volatile memory bit cell candidates are emerging which can be implemented between two metal layers in the BEOL process. Thus, short flow Characterization Vehicle® (CV®) Test Chips become beneficial for fast yield and endurance lea
Autor:
Larg Weiland, Bing-Yue Tsui
Publikováno v:
2016 International Conference on Microelectronic Test Structures (ICMTS).
Publikováno v:
IEEE Transactions on Semiconductor Manufacturing. 16:259-265
Complexity of integrated circuits has led to many millions of contacts and vias on every chip. To allow accurate yield evaluation, it is required to determine fail rates of < 10 faults per billion which requires test structures with huge chains of 1
Autor:
Larg Weiland, Hans Eisenmann, Amit Joag, Kelvin Doong, Scott Lin, Sa Zhao, Balasubramania Murugan, Christopher Hess
Publikováno v:
2014 International Conference on Microelectronic Test Structures (ICMTS).
Due to recent changes in the manufacturing of FEOL (front end of line) layers it is increasingly difficult to provide rapid learning cycles required to drive yield improvement during new product introduction (NPI). The Direct Probe Characterization V
Autor:
Sunnys Hsieh, Che-Hsiung Hsu, Larg Weiland, Ding-Ming Kwai, Kelvin Doong, Jye-Yen Cheng, Christopher Hess, Binson Shen, Sheng-Che Lin
Publikováno v:
IEEE Transactions on Semiconductor Manufacturing. 14:338-355
As technologies scale down, semiconductor manufacturing processes require more and more areas for test structures to ensure accurate yield estimation. This paper presents design guidelines for test structures with addressable failure sites to efficie
Autor:
Larg Weiland, Christopher Hess, K. Miyamoto, D. Stashower, Gaurav Verma, K. Inoue, Brian E. Stine
Publikováno v:
IEEE Transactions on Semiconductor Manufacturing. 14:330-337
Defect inspection is required for process control and to enhance chip yield. Electrical measurements of test structures are commonly used to detect faults. To improve accuracy of electrically based determination of defect densities and defect size di
Autor:
Larg Weiland, Christopher Hess
Publikováno v:
IEEE Transactions on Semiconductor Manufacturing. 12:175-183
Defect density distributions play an important role in process control and yield prediction. To improve yield prediction we present a methodology to extract wafer-level defect density distributions better reflecting such chip-to-chip defect density v