Výsledky vyhledávání - "Lan-chou Cho"

Dissertation/ Thesis

Clock Generator and Burst-Mode CDR for Optical Communications

Autor: Lan-Chou Cho, 卓聯洲

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With the development and advancement of technology, the more and more data transmission quantity is needed. High-speed and long-distance communication systems mostly adopt the optical networks in various applications. The clock generator for

Externí odkaz: http://ndltd.ncl.edu.tw/handle/00637059412805793523

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A 0.85mm2 51%-Efficient 11-dBm Compact DCO-DPA in 16-nm FinFET for Sub-Gigahertz IoT TX Using HD2 Self-Suppression and Pulling Mitigation

Autor: Huan-Neng Ron Chen, Mark Chen, Lan-Chou Cho, Feng Wei Kuo, Chewn-Pu Jou, Robert Bogdan Staszewski, Kai Xu

Publikováno v: IEEE Journal of Solid-State Circuits. 54:2028-2037

In this paper, we propose a sub-gigahertz transmitter (TX) with a physically merged digitally controlled oscillator (DCO) and digital power amplifier (DPA). The matching transformer of single-ended DPA is placed inside the DCO transformer to save ~50

Externí odkaz: https://explore.openaire.eu/search/publication?articleId=doi_________::84f813a53348bc749a6c7c3e262cd069
https://doi.org/10.1109/jssc.2019.2906803

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An All-Digital PLL for Cellular Mobile Phones in 28-nm CMOS with −55 dBc Fractional and −91 dBc Reference Spurs

Autor: Feng Wei Kuo, Masoud Babaie, Lan-Chou Cho, Huan-Neng Ron Chen, Mark Chen, Chewn-Pu Jou, Robert Bogdan Staszewski

Publikováno v: IEEE Transactions on Circuits and Systems Part 1: Regular Papers, 65(11)

We propose a time-predictive architecture of an all-digital PLL (ADPLL) for cellular radios, which is optimized for advanced CMOS. It is based on a 1/8-length time-to-digital converter (TDC) of stabilized 7-ps resolution, as well as wide tuning range

Externí odkaz: https://explore.openaire.eu/search/publication?articleId=doi_dedup___::d405eada66a85642ac84733bc60a59c1
https://doi.org/10.1109/tcsi.2018.2855972

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A 77/79-GHz Frequency Generator in 16-nm CMOS for FMCW Radar Applications Based on a 26-GHz Oscillator with Co-Generated Third Harmonic

Autor: Robert Bogdan Staszewski, Lan-Chou Cho, Chewn-Pu Jou, Huan-Neng Ron Chen, Mark Chen, Zhirui Zong, Feng Wei Kuo

Publikováno v: ESSCIRC
ESSCIRC 2019-IEEE 45th European Solid State Circuits Conference

This paper presents a digitally controlled frequency generator for dual frequency-band radar system that is optimized for 16 nm FinFET CMOS. It is based on a 21% wide tuning range,fine-resolution DCO with only switchable metal capacitors. A third-har

Externí odkaz: https://explore.openaire.eu/search/publication?articleId=doi_dedup___::8cb29643e1389f8438dccf55c523d67c
https://doi.org/10.1109/esscirc.2019.8902490

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Towards Ultra-Low-Voltage and Ultra-Low-Power Discrete-Time Receivers for Internet-of-Things

Autor: Masoud Babaie, Ron Chen, Feng Wei Kuo, Lan-Chou Cho, Chewn-Pu Jou, Robert Bogdan Staszewski, Mark Chen, Sandro Binsfeld Ferreira

Publikováno v: 2018 IEEE/MTT-S International Microwave Symposium - IMS.

In this paper, we investigate an impact of voltage supply scaling on power consumption and performance of a new class of wireless receivers (RX) for Internet-of-Things (IoT) applications: a discrete-time (DT) superheterodyne architecture realized in

Externí odkaz: https://explore.openaire.eu/search/publication?articleId=doi_________::5d4e6da3ebb4243af14ed3d53e1ddc12
https://doi.org/10.1109/mwsym.2018.8439369

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A 0.5V 1.6mW 2.4GHz fractional-N all-digital PLL for Bluetooth LE with PVT-insensitive TDC using switched-capacitor doubler in 28nm CMOS

Autor: Feng Wei Kuo, Teerachot Siriburanon, Fu-Lung Hsueh, Ron Chen, Lan-Chou Cho, Pourmousavian Seyednaser, Chewn-Pu Jou, Robert Bogdan Staszewski

Publikováno v: 2017 Symposium on VLSI Circuits.

This paper proposes an ultra-low-voltage (ULV) fractional-N all-digital PLL (ADPLL) powered from a single 0.5 V supply. While its DCO runs directly at 0.5 V, a switched-capacitor DC-DC converter doubles the supply voltage to all the digital circuitry

Externí odkaz: https://explore.openaire.eu/search/publication?articleId=doi_________::28ed31b146a46ba5744a9f79e22a3074
https://doi.org/10.23919/vlsic.2017.8008472

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A 4GHz clock distribution architecture using subharmonically injection-locked coupled oscillators with clock skew calibration in 16nm CMOS

Autor: Jack Liu, Feng Wei Kuo, Fu-Lung Hsueh, Lan-Chou Cho, Chewn-Pu Jou, R. Bogdan Staszewski, Ron Chen

Publikováno v: 2017 Symposium on VLSI Circuits.

We propose a new approach to an on-chip clock distribution scheme. It is based on distributed multi-GHz LC-tank oscillators generating local clocks. The oscillators are mutually coupled to align their frequencies and are further subharmonically injec

Externí odkaz: https://explore.openaire.eu/search/publication?articleId=doi_________::2f230d0fc8c3636980baaf95fffc396e
https://doi.org/10.23919/vlsic.2017.8008457

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A Bluetooth Low-Energy Transceiver with 3.7-mW All-Digital Transmitter, 2.75-mW High-IF Discrete-Time Receiver, and TX/RX Switchable On-Chip Matching Network

Autor: Mina Shahmohammadi, Sandro Binsfeld Ferreira, Fu-Lung Hsueh, Iman Madadi, Masoud Babaie, Chewn-Pu Jou, Robert Bogdan Staszewski, Massoud Tohidian, Huan-Neng Ron Chen, Feng Wei Kuo, Lan-Chou Cho

Publikováno v: IEEE Journal of Solid State Circuits, 52(4)

We present an ultra-low-power Bluetooth low-energy (BLE) transceiver (TRX) for the Internet of Things (IoT) optimized for digital 28-nm CMOS. A transmitter (TX) employs an all-digital phase-locked loop (ADPLL) with a switched current-source digitally

Externí odkaz: https://explore.openaire.eu/search/publication?articleId=doi_dedup___::189570f7103b05c17323c5659e6da986
http://resolver.tudelft.nl/uuid:f11ffeac-beee-43bc-ab3d-b21779ca77b3

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A Bluetooth low-energy (BLE) transceiver with TX/RX switchable on-chip matching network, 2.75mW high-IF discrete-time receiver, and 3.6mW all-digital transmitter

Autor: Massoud Tohidian, Sandro Binsfeld Ferreira, Fu-Lung Hsueh, Robert Bogdan Staszewski, Iman Madadi, Chewn-Pu Jou, Masoud Babaie, Ron Chen, Feng Wei Kuo, Guanzhong Huang, Lan-Chou Cho

Publikováno v: VLSI Circuits

We present a new ultra-low-power (ULP) transceiver for Internet-of-Things (IoT) optimized for 28-nm CMOS. The receiver (RX) employs a high-rate (up to 10 GS/s) discrete-time (DT) architecture with intermediate frequency (IF) placed beyond the 1/f noi

Externí odkaz: https://explore.openaire.eu/search/publication?articleId=doi_________::32ca7b468c6f4fe65580bb217d9cbeb5
https://doi.org/10.1109/vlsic.2016.7573480

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All-Digital Phase-Locked Loop

Autor: Lan-Chou Cho, Kuang-Kai Yen, Tsung-Hsiung Lee, Robert Bogdan Staszewski, Feng Wei Kuo, Huan-Neng Chen, Chewn-Pu Jou

Publikováno v: All-Digital Frequency Synthesizer in Deep-Submicron CMOS

A circuit and a method are disclosed herein. The circuit includes a digitally controlled oscillator and a detector. The digitally controlled oscillator is configured to generate an oscillator signal according to an oscillator tuning word. The detecto

Externí odkaz: https://explore.openaire.eu/search/publication?articleId=doi_________::f512f9aa8e6cacfa4c50dfc9a389ccf9
https://doi.org/10.1016/b978-0-12-802207-8.00004-6

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