Zobrazeno 1 - 5
of 5
pro vyhledávání: '"Lalinda D. Fernando"'
Publikováno v:
IEEE Journal of Solid-State Circuits. 53:1481-1492
This paper presents a passive-charge-sharing successive approximation register (SAR) analog-to-digital converter (ADC) that achieves 16-bit linearity. It is known that on-chip passive charge sharing suffers from poor linearity due to the unregulated
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::435188389695906a3e770916aa6b540e
https://doi.org/10.1109/jssc.2018.2793558
https://doi.org/10.1109/jssc.2018.2793558
Publikováno v:
ISCAS
This paper proposes an adaptive algorithm for a predicting SAR ADC which can self-adjust the precision of its prediction. A precise and yet correct prediction reduces bit trials needed in a SAR conversion, leading to great power savings. The presente
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::85ed1bcc65f96c53eb8071b744557ac8
https://doi.org/10.1109/iscas.2018.8351143
https://doi.org/10.1109/iscas.2018.8351143
Autor:
Mark D. Maddox, Ned Guthrie, Michael C. W. Coln, Nikhil Mascarenhas, Ron Kapusta, Lalinda D. Fernando, Junhua Shen, Baozhen Chen, Akira Shikata
Publikováno v:
2017 Symposium on VLSI Circuits.
This paper presents a successive approximation register (SAR) analog-to-digital converter (ADC) that is much smaller and faster than other recently reported precision (16-bit and beyond) SAR ADCs. In addition, it features low input capacitance and an
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_dedup___::1de2e74a04519126301a8684ea260ed7
https://doi.org/10.23919/vlsic.2017.8008509
https://doi.org/10.23919/vlsic.2017.8008509
Autor:
Michael C. W. Coln, Baozhen Chen, Mark D. Maddox, Lalinda D. Fernando, Junhua Shen, Ron Kapusta
Publikováno v:
A-SSCC
This paper presents a first reported passive-charge-sharing SAR ADC that achieves 16 bit linearity. It is known that on chip passive-charge-sharing suffers from poor linearity due to the unregulated reference voltage during bit trials. The proposed u
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::63d4a87b55e24eac7157f77d1e3a5343
https://doi.org/10.1109/asscc.2016.7844158
https://doi.org/10.1109/asscc.2016.7844158
Publikováno v:
IEEE Journal of Solid-State Circuits. 53:1869-1869
In the above paper [1] , one co-author was mistakenly left out of the byline. The correct byline and Junhua Shen’s biography and photograph are as follows.
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::79eddc21b56fb087712ee57c28e5f8d0
https://doi.org/10.1109/jssc.2018.2831878
https://doi.org/10.1109/jssc.2018.2831878