Zobrazeno 1 - 10
of 10
pro vyhledávání: '"Lakshminarayanan Renganarayana"'
Autor:
Niyu Ge, Jiaqi Zhang, Xiaolan Zhang, Yuanyuan Zhou, Vasanth Bala, Tianyin Xu, Lakshminarayanan Renganarayana
Publikováno v:
ASPLOS
As software systems become more complex and configurable, failures due to misconfigurations are becoming a critical problem. Such failures often have serious functionality, security and financial consequences. Further, diagnosis and remediation for s
Publikováno v:
RACES@SPLASH
Synchronization overhead is a major bottleneck in scaling parallel applications to a large number of cores. This continues to be true in spite of various synchronization-reduction techniques that have been proposed. Previously studied synchronization
Autor:
Marco A. S. Netto, John J. Rofrano, Christopher Ward, Brian Peterson, Marcos Dias De Assuncao, Lakshminarayanan Renganarayana, Christopher C. Young
Publikováno v:
NOMS
Increasingly organizations are considering moving their workloads to clouds to take advantage of the anticipated benefits of a more cost effective and agile IT infrastructure. A key component of a cloud service, as it is exposed to the consumer, is t
Autor:
Ling Shao, John Kevin Patrick O'Brien, Tong Chen, Huoding Li, Tao Liu, Haibo Lin, Lakshminarayanan Renganarayana
Publikováno v:
PACT
In this paper we present the design and implementation of a DMATiler which combines compiler analysis and runtime management to optimize local memory performance. In traditional cache model based loop tiling optimizations, the compiler approximates r
Autor:
Alexandre E. Eichenberger, Uday Bondhugula, Salem Derisavi, Kevin O'Brien, Lakshminarayanan Renganarayana
Publikováno v:
SC
To achieve high performance on multi-cores, modern loop optimizers apply long sequences of transformations that produce complex loop structures. Downstream optimizations such as register tiling (unroll-and-jam plus scalar promotion) typically provide
Publikováno v:
IPDPS
Stencil computations form the performance-critical core of many applications. Tiling and parallelization are two important optimizations to speed up stencil computations. Many tiling and parallelization strategies are applicable to a given stencil co
Publikováno v:
Languages and Compilers for Parallel Computing ISBN: 9783540693291
LCPC
LCPC
Efficient use of multiple pipelined functional units and registers is very important for achieving high performance on modern processors. Instruction Level Parallelism (ILP) and register reuse (through register tiling) are two mechanisms for this, re
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::3baa4609312a3fd095c80624d2e177c8
https://doi.org/10.1007/978-3-540-69330-7_17
https://doi.org/10.1007/978-3-540-69330-7_17
Publikováno v:
SC
Determining the optimal tile size-one that minimizes the execution time-is a classical problem in compilation and performance tuning of loop kernels. Designing a model of the overall execution time of a tiled loop nest is an important subproblem. Bot
Publikováno v:
2007 IEEE International Parallel & Distributed Processing Symposium; 2007, p1-10, 10p