Zobrazeno 1 - 10
of 45
pro vyhledávání: '"L.T. Pillage"'
Publikováno v:
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems. 13:729-736
Asymptotic Waveform Evaluation (AWE) has been demonstrated as an efficient approach for interconnect circuit simulation/analysis. However, since it is based upon moment-matching, it is prone to yielding unstable approximations for stable circuits. Th
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::7b8fc89aed0439e314069e20939cb4c1
https://doi.org/10.1109/43.285247
https://doi.org/10.1109/43.285247
Autor:
L.T. Pillage, C.L. Ratzlaff
Publikováno v:
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems. 13:763-776
This paper describes the Rapid Interconnect Circuit Evaluator (RICE) software developed specifically to analyze RC and RLC interconnect circuit models of virtually any size and complexity. RICE focuses specifically on the passive interconnect problem
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::124c3520788f240b64141eab485e5cd4
https://doi.org/10.1109/43.285250
https://doi.org/10.1109/43.285250
Publikováno v:
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems. 13:1257-1270
This paper presents a method of obtaining time-domain macromodels of VLSI interconnection networks for circuit simulation. The goal of this work is to include interconnect parasitics in a circuit simulation as efficiently as possible, without signifi
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::b2a373cee596dd46e88ce9d49a5a4bb9
https://doi.org/10.1109/43.317469
https://doi.org/10.1109/43.317469
Autor:
L.T. Pillage
Publikováno v:
IEEE Transactions on Education. 36:16-19
It is argued that introducing simulation tools such as SPICE at the undergraduate level can sometimes cause the students to lack an appreciation for circuit theory and solving circuits. Some undergraduates question the need to solve circuit problems
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::bc5032d78fd6666a366ed5283613dafa
https://doi.org/10.1109/13.204809
https://doi.org/10.1109/13.204809
Autor:
L.T. Pillage, R.A. Rohrer
Publikováno v:
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems. 9:352-366
Asymptotic waveform evaluation (AWE) provides a generalized approach to linear RLC circuit response approximations. The RLC interconnect model may contain floating capacitors, grounded resistors, inductors, and even linear controlled sources. The tra
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::774d21e72158b99da8966f332695dc0c
https://doi.org/10.1109/43.45867
https://doi.org/10.1109/43.45867
Publikováno v:
Proceedings of 1993 International Conference on Computer Aided Design (ICCAD).
Recenily, seveml design auiomaiion approaches for delay and skew minimization of clock nets have been proposed. These approaches are based upon varying the widths and lengths of the clock tree wires io minimize skew and sometimes delay. Most of these
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::853567a6d37c47658b029cfc3f3fdb1a
https://doi.org/10.1109/iccad.1993.580114
https://doi.org/10.1109/iccad.1993.580114
Publikováno v:
IEEE/ACM International Conference on Computer-Aided Design.
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::deecea17fbfc6bb8e22c46745884b799
https://doi.org/10.1109/iccad.1994.629837
https://doi.org/10.1109/iccad.1994.629837
Publikováno v:
[1992 Proceedings] Electrical Performance of Electronic Packaging.
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::b553bfa8c9bb4006b870609085e6f3f8
https://doi.org/10.1109/epep.1992.572283
https://doi.org/10.1109/epep.1992.572283
Publikováno v:
Proceedings of the IEEE Custom Integrated Circuits Conference.
An approach for accurately modeling the RC-interconnect delay and gate-loading effects in a hierarchical timing analyzer is presented. The change in gate-loading due to interconnect resistance is considered by an "effective capacitance" approximation
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::1ff332cea13145588b67f8e4e18656b6
https://doi.org/10.1109/cicc.1992.591314
https://doi.org/10.1109/cicc.1992.591314
Publikováno v:
[1992] Proceedings 29th ACM/IEEE Design Automation Conference.
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::f0120ff22eb13d56381a06b47271a808
https://doi.org/10.1109/dac.1992.227835
https://doi.org/10.1109/dac.1992.227835