Zobrazeno 1 - 10
of 29
pro vyhledávání: '"L.S. Driscoll"'
Autor:
L.S. Driscoll, Anthony O'Neill, Douglas J. Paul, Sarah H. Olsen, Sanatan Chattopadhyay, K.S.K. Kwa, Matthew J. Temple
Publikováno v:
Thin Solid Films. 508:338-341
The benefit of high performance strained Si CMOS in terms of technology generations is quantified. It is shown that a 0.3 μm gate length strained Si/Si 0.75 Ge 0.25 CMOS technology has the same gate delay as conventional technology having an effecti
Autor:
Anthony O'Neill, A. G. Cullis, Sarah H. Olsen, D. J. Norris, L.S. Driscoll, Sanatan Chattopadhyay, Douglas J. Paul, K.S.K. Kwa
Publikováno v:
IEEE Transactions on Electron Devices. 51:1245-1253
Results comparing strained-Si-SiGe n-channel MOSFET performance of single-and dual-surface channel devices fabricated using 15% Ge content SiGe virtual substrates are presented. Device fabrication used high thermal budget processes and virtual substr
Autor:
K.S.K. Kwa, L.S. Driscoll, Anthony O'Neill, Jing Zhang, Sarah H. Olsen, Sanatan Chattopadhyay, A.M. Waite, Y.T. Tang, A.G.R. Evans
Publikováno v:
IEEE Transactions on Electron Devices. 51:1156-1163
On-state and off-state performance of strained-Si-SiGe n-channel MOSFETs have been investigated as a function of SiGe virtual substrate alloy composition. Performance gains in terms of on-state drain current and maximum transconductance of up to 220%
Autor:
Steve Bull, K.S.K. Kwa, Sanatan Chattopadhyay, D. J. Norris, A.M. Waite, Y.T. Tang, L.S. Driscoll, A.G.R. Evans, Anthony O'Neill, A. G. Cullis, Sarah H. Olsen
Publikováno v:
Materials Science and Engineering: B. 109:78-84
The performance of surface channel MOS devices depends on gate oxide interface quality. Carrier transport is enhanced in strained Si, thus its use for MOSFET channels can increase device performance. Thermal oxidation produces the highest quality Si0
Autor:
K.S.K. Kwa, D. J. Robbins, L.S. Driscoll, Sarah H. Olsen, D. J. Norris, Jing Zhang, A. G. Cullis, Anthony O'Neill, Sanatan Chattopadhyay
Publikováno v:
Semiconductor Science and Technology. 19:707-714
The enhanced electrical performance of dual quantum well strained Si/SiGe n-channel MOSFETs has been investigated as a function of SiGe material quality. The higher electron mobility in strained Si compared with bulk Si has been translated into perfo
Autor:
D. J. Robbins, K.S.K. Kwa, L.S. Driscoll, V. Higgs, Jing Zhang, Sanatan Chattopadhyay, Sarah H. Olsen, Anthony O'Neill
Publikováno v:
Journal of Applied Physics. 94:6855-6863
Strained Si/SiGe n-channel metal-oxide-semiconductor field-effect transistors (MOSFETs) have been fabricated using a dual quantum well structure. The heterostructure is designed for maximum performance from both n- and p-channel devices using a singl
Publikováno v:
Semiconductor Science and Technology. 18:738-744
Capacitance–voltage (C–V) characteristics are used to investigate double heterojunction strained Si/SiGe MOS capacitors. Structures of this type potentially form the channels of CMOS devices based on the strained Si/SiGe material system. The tech
Autor:
Anthony O'Neill, Sarah H. Olsen, Sanatan Chattopadhyay, K.S.K. Kwa, L.S. Driscoll, Nebojsa Jankovic
Publikováno v:
Semiconductor Science and Technology. 18:82-87
A capacitance model is developed and a correction formula is derived to reconstruct the intrinsic oxide capacitance value from measured capacitance and conductance of lossy MOS devices. Due to discrepancies during processing, such as cleaning, an unw
Autor:
S. Chattopadhay, Jing Zhang, K.S.K. Kwa, Anthony O'Neill, L.S. Driscoll, Douglas J. Paul, Sarah H. Olsen
Publikováno v:
International Semiconductor Device Research Symposium, 2003.
The performance of single and dual channel strained Si n-MOSFETs fabricated using CMOS process. A TEM image of the strained Si/gate oxide interface was examined. Capacitance-voltage measurement on MOS capacitor was investigated. The gate oxide interf
Publikováno v:
Electrical Performance of Electrical Packaging (IEEE Cat. No. 03TH8710).
It is demonstrated from experimental I-V and C-V data, and confirmed by computer simulation, that strained Si/SiGe MOSFET performance severely degrades below a channel thickness of 7 nm. MOSFETs with strained Si channels of thickness 5 nm, 7 nm and 9