Zobrazeno 1 - 10
of 30
pro vyhledávání: '"L. Vishnubhotla"'
Autor:
L. Vishnubhotla, Pierre Morin, Robert Fox, S. Boret, R. Difrenza, B. Tavel, K. Rochereau, P. Stolk, C. Detcheverry, Daniel Gloria, M.T. Basso, M. Woo, M. Broekaart, B. Duriez, P. Garnier, D. Reber, Y. Trouille, J. Bienacel, M. Denais, D. Barge, C. Ortolland, K. Cooper, Frederic Boeuf, S. Vanbergue, Vincent Huard, Jean-Damien Chapon, J. Belledent, Pascal Gouraud, Nicolas Planes, Franck Arnaud, P. Abramowitz, E. Saboure, Y. Laplanche, C. Julien, M. Bidaud, M. Marin, Romain Gwoziecki
Publikováno v:
Solid-State Electronics. 50:573-578
A complete 65 nm CMOS platform, called LP/GP Mix, has been developed employing thick oxide transistor (IO), Low Power (LP) and General Purpose (GP) devices on the same chip. Dedicated to wireless multi-media and consumer applications, this new triple
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_dedup___::2a1f438c93e06660abf827ae1f1027bf
https://doi.org/10.1016/j.sse.2006.03.030
https://doi.org/10.1016/j.sse.2006.03.030
Autor:
J. Bienacel, Kathy Barla, D. Roy, M. Bidaud, L. Vishnubhotla, N. Emonet, D. Barge, I. Pouilloux
Publikováno v:
Materials Science in Semiconductor Processing. 7:181-183
Plasma nitridation of thermally grown oxide films has proven to be an excellent gate dielectric in meeting the electrical requirements of the 65 nm node. As the 65 nm device performance is very sensitive to both physical thickness and nitrogen dose o
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::a76648bfcbc2be3991a6dce859fa179a
https://doi.org/10.1016/j.mssp.2004.09.014
https://doi.org/10.1016/j.mssp.2004.09.014
Publikováno v:
Microelectronic Engineering. 22:97-100
The incorporation of fluorine in the gate oxide is shown to reduce interface defect density in (100) and (111) Si MOSFETs, leading to increased carrier mobility and reduced 1/f noise. The resulting low densities of interface traps and oxide charge ha
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::7a6d623093d298d6ffa32d5ba88baee7
https://doi.org/10.1016/0167-9317(93)90139-v
https://doi.org/10.1016/0167-9317(93)90139-v
Autor:
F. Arnaud, M. Bidaud, G. Ribes, Vincent Huard, Chittoor Parthasarathy, Alain Bravaix, F. Perrier, P. Stolk, L. Vishnubhotla, M. Denais, David Barge, B. Tavel, Nathalie Revil, Y. Rey-Tauriac
Publikováno v:
IEEE International Integrated Reliability Workshop Final Report, 2004.
We have developed in this work a new characterization methodology which includes stressing and measurement in a single experimental step. This overcomes the influence of the hole detrapping effect in ultra-thin gate-oxides (T/sub OX/=1.4-1.6 nm) and
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::e1c1d2cd245379949963fb451823b594
https://doi.org/10.1109/irws.2004.1422753
https://doi.org/10.1109/irws.2004.1422753
Autor:
D. Dyer, D. Wristers, P. Ingersoll, Karl Wimmer, R. Stout, John R. Alvis, Yongjoo Jeon, P. Grudowski, J. Conner, D. Bonser, P. Abramowitz, T.V. Gompel, J. Pellerin, J.J. Lee, A. Duvallet, M. Foisy, K. Hellig, S. Lim, D. Hall, L. Vishnubhotla, S. Parihar, A. Nghiem, G.C.-F. Yeap, Kyle Patterson, W. Qi, M. Rendon, Yang Du, Y. Shiho, J. Chen, S. Jallepalli, Marilyn Irene Wright, K. Weidemann, M. Woo, David Burnett, T. Luo, Craig S. Lage, R. Singh, C. Reddy, M. Hall, H.-H. Tseng, S. Veeraraghavan, N. Benavides, N. Ramani
Publikováno v:
Scopus-Elsevier
We report a 100 nm modular bulk CMOS technology platform with multi Vt and multi gate oxide integrated transistors that enables device and circuit co-design (M. Fukuma et al., VLSI Tech., 2000) techniques (e.g. well biasing and power down/reduction)
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_dedup___::0a237a9f8ada06ab05722eb1c2d43b26
https://doi.org/10.1109/vlsit.2002.1015370
https://doi.org/10.1109/vlsit.2002.1015370
Publikováno v:
1993 International Symposium on VLSI Technology, Systems, and Applications Proceedings of Technical Papers.
By introducing appropriate amounts of F into the gate SiO/sub 2/, the transconductance and channel mobility for both n- and p-channel MOSFETs made on either (100) or (111) Si substrate are improved, due to the reduced densities of interface traps and
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::49725fdc18a4298ba928f9279342ad11
https://doi.org/10.1109/vtsa.1993.263635
https://doi.org/10.1109/vtsa.1993.263635
Autor:
Janice C. Molloy, M. Wright, L. Parker, D. Smith, C. Lage, M. Wilson, G. Yeap, T. Van Gompel, L. Terpolilli, M. Angyal, N. Ramani, R. Ross, S. Parihar, R. Pena, P. Le, S. Roling, D. Rose, Y. Jeon, R. Li, M. Turner, B. Boeck, T. Stephens, B. Wilson, M. Hall, A. Phillips, Y. Solomentsev, K. Junker, S. Filipiak, J. Schmidt, P. Grudowski, M. Woo, V. Arunachalam, K. McGuffin, K. Strozewski, A. Michel, M. Smith, M. Aminpur, R. Mora, K. Hellig, X. Bai, D. Reber, L. Vishnubhotla, F. Huang, J. Chen, J. Sun, K. Yu, W. Qi, P. Ingersoll, A. Singhal, M. Rendon, T. Sparks
Publikováno v:
International Electron Devices Meeting. Technical Digest (Cat. No.01CH37224).
In this work components of the next generation 0.10 /spl mu/m CMOS technology are presented. They form the core of a platform encompassing logic, non volatile memory, and analog blocks. High performance bulk devices use 18 /spl Aring/ gate oxide (24
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::8de3a0d37c15c9ef5f6dfc5e0723cab8
https://doi.org/10.1109/iedm.2001.979477
https://doi.org/10.1109/iedm.2001.979477
Autor:
G. Williamson, P. Lysaght, Peter Zeitzoff, Billy Nguyen, S. Kim, Kenneth Torres, V.H.C. Watt, J. A. Fair, G. Gale, M.D. Jackson, M. C. Gilmer, T. Y. Luo, George A. Brown, Carolyn F. H. Gondran, M. T. Schulberg, T. Tamagawa, Gennadi Bersuker, R. Amos, Howard R. Huff, D. Brady, Franz T. Geyling, J. Guan, L. Vishnubhotla
Publikováno v:
MRS Proceedings. 567
A design-of-experiments methodology was implemented to assess the commercial equipment viability to fabricate the high-K dielectrics Ta2O5, TiO2 and BST (70/30 and 50/50 compositions) for use as gate dielectrics. The high-K dielectrics were annealed
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::0e0a21e1ee9f5cd28e4f9fbe0838ad4d
https://doi.org/10.1557/proc-567-323
https://doi.org/10.1557/proc-567-323
Autor:
Howard R. Huff, F. Shaapur, Kenneth Torres, Alain C. Diebold, A. Karamcheti, Peter Zeitzoff, X. Guo, L. Vishnubhotla, V.H.C. Watt, Gennadi Bersuker, T. Tamagawa, J. Guan, Xiaomu Wang, D. Brady, M.D. Jackson, George A. Brown, T. Y. Luo, Tso-Ping Ma, M. C. Gilmer, G. Gale
Publikováno v:
MRS Proceedings. 592
This paper describes the electrical and physical characteristics of ultrathin Jet Vapor Deposited (JVD) Silicon Oxynitride films. Capacitance-Voltage measurements indicate an equivalent oxide thickness (EOT) of less than 2 nm, taking into account the
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::022a80a5bdcaebde1885916b3f31a4d8
https://doi.org/10.1557/proc-592-307
https://doi.org/10.1557/proc-592-307
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