Zobrazeno 1 - 10
of 65
pro vyhledávání: '"L. Sumanen"'
Autor:
Tero Tikka, L. Sumanen, Ville Saari, Jussi Ryynanen, Kari Halonen, Jarkko Jussila, A. Malinen, M. Hotti
Publikováno v:
IEEE Journal of Solid-State Circuits. 41:1542-1550
The multicarrier receiver IC described in this paper receives four adjacent WCDMA channels simultaneously in order to reduce the component count of a base-station. The receiver uses low-IF architecture and it is fabricated with a 0.25-mum SiGe BiCMOS
Publikováno v:
Analog Integrated Circuits and Signal Processing. 46:17-27
This article presents a 14-bit, 100-MS/s time-interleaved pipeline ADC, which samples input signal from 210-MHz IF-band. Digital self-calibration is employed to compensate gain mismatch and offset between time-interleaved channels as well as mismatch
Publikováno v:
IEEE Transactions on Circuits and Systems II: Express Briefs. 52:636-640
A low-power embedded SRAM for a large range of applications has been implemented in a standard digital 0.18-/spl mu/m process. The leakage current in the cells is reduced by using a source-body bias not exceeding the value that guaranties safe data r
Publikováno v:
IEEE Journal of Solid-State Circuits. 38:594-602
A single-chip, multimode receiver for GSM900, DCS1800, PCS1900, and UTRA/FDD WCDMA is introduced in this paper. The receiver operates at four different radio frequencies with two different baseband bandwidths. The presented chip uses a direct-convers
Publikováno v:
Analog Integrated Circuits and Signal Processing. 35:33-45
A 14-bit current-steering DAC utilizing parallel current memories operating as a deglitcher is presented. The high linearity of the current memories is based on a memory MOS transistor biased in the triode region and a bootstrapped sampling switch. T
Publikováno v:
Analog Integrated Circuits and Signal Processing. 37:201-213
A 13b 50MSample/s pipeline ADC with digital self-calibration and IF-sampling frontend, using a 0.35/spl mu/m BiCMOS process, achieves 76.5dB SFDR at 194MHz input. The chip occupies 6mm/sup 2/ and dissipates 715mW from a 2.9V supply.
Publikováno v:
IEEE Journal of Solid-State Circuits. 36:1048-1055
This paper describes a 10-bit 200-MS/s CMOS parallel pipeline analog-to-digital (A/D) converter that can sample input frequencies above 200 MHz. The converter utilizes a front-end sample-and-hold (S/H) circuit and four parallel interleaved pipeline c
Publikováno v:
IEEE Journal of Solid-State Circuits. 36:2025-2029
A 2-GHz single-chip direct conversion receiver achieves a 3.0-dB double-sideband noise figure, -14-dBm IIP3 and +17-dBm IIP2 with 60-mW power consumption from a 2.7-V supply. The receiver is targeted for the third generation UTRA/FDD WCDMA system. Th
Publikováno v:
Analog Integrated Circuits and Signal Processing. 22:41-49
This paper describes an 8-bit 40 MS/s pipeline A/D converter suitable for WCDMA receiver applications. Small power consumption is achieved by using 1.5 bit/stage pipeline architecture and by scaling the capacitor values along the converter. Digital c
Publikováno v:
Analog Integrated Circuits and Signal Processing. 18:55-67
A quadrature baseband frequency synthesizer/modulator IC has been designed and fabricated in a 0.5 μm CMOS. This quadrature baseband frequency synthesizer/modulator is intended for use in a wide variety of indoor/outdoor portable wireless applicatio