Zobrazeno 1 - 10
of 43
pro vyhledávání: '"L. Pinzelli"'
Autor:
Eric G. L. Pinzelli
In Masters of Warfare, Eric G. L. Pinzelli presents a selection of fifty commanders whose military achievements, skill or historical impact he believes to be underrated by modern opinion. He specifically does not include the household names (the'Gods
Autor:
Vincent Lu, Fuccio Cristiano, Denis Rideau, Remi Beneyton, Nicolas Guitard, Marc Juhel, Edwin Arevalo, Wei Zou, C. Borowiak, Thomas Nassiet, Frederic Monsieur, E. Ghegin, L. Pinzelli, J. Borrel, K. Dabertrand, Romain Duru, L. Clément, Evan Oudot, Sylvain Joblot
Publikováno v:
2018 22nd International Conference on Ion Implantation Technology (IIT).
In this work, heated implantation impact on defect generation is observed for non-amorphizing conditions and specific anneal. Photoluminescence imaging method has been used and exhibits radiative defect density variation with chuck temperature. Moreo
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::d058f5e1559ff993fd38f7318711151b
https://doi.org/10.1109/iit.2018.8807957
https://doi.org/10.1109/iit.2018.8807957
Autor:
Arnaud Tournier, L. Pinzelli, Francois Roy, D. Jeanjean, S. Hulot, F. Blanchet, Laurent Favennec, Didier Herault, C. Perrot, Francois Leverd, J.-P. Carrere, Helene Wehbe-Alause, S. Ricq, N. Cherault, P. Boulenc, C. Augier, Maxime Gatefait
Publikováno v:
physica status solidi c. 11:50-56
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::4ccb5297020f5ce92bdc127d234e5ce2
https://doi.org/10.1002/pssc.201300378
https://doi.org/10.1002/pssc.201300378
Challenges and opportunity in performance, variability and reliability in sub-45nm CMOS technologies
Publikováno v:
Microelectronics Reliability. 51:1508-1514
In this paper, we present a detailed discussion related to the consequences on CMOS process flow for the high-speed race required by electronics applications. Key process elements for CMOS circuits speed enhancement are reported such as process stres
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::35b32756f5e6e5f2315e60d2c9c90742
https://doi.org/10.1016/j.microrel.2011.06.059
https://doi.org/10.1016/j.microrel.2011.06.059
Autor:
Loan Pham-Nguyen, Stephane Denorme, P. Gros, Pascal Gouraud, Pierre Perreau, Sébastien Barnola, Sebastien Haendler, A. Margain, Y. Campidelli, F. Boedt, Olivier Weber, Christian Arvet, Daniel Delprat, J. Vetier, Francois Leverd, Remi Beneyton, C. Fenouillet-Beranger, C. Perrot, Tomasz Skotnicki, Stephane Monfray, Bich-Yen Nguyen, O. Faynot, F. Baron, Konstantin Bourdelle, C. de Buttet, A. Torres, Francois Andrieu, L. Pinzelli, L. Tosti, C. Borowiak, C. Laviron, F. Abbate
Publikováno v:
Solid-State Electronics. 54:849-854
In this paper we explore for the first time the impact of an ultra-thin BOX (UTBOX) with and without ground plane (GP) on a 32 nm fully-depleted SOI (FDSOI) high-k/metal gate technology. The performance comparison versus thick BOX architecture exhibi
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::a64d2a50140eb30c48a51e6e373d86d6
https://doi.org/10.1016/j.sse.2010.04.009
https://doi.org/10.1016/j.sse.2010.04.009
Publikováno v:
Thin Solid Films. 518:2390-2393
Due to the continuous CMOS transistor scaling requirements, highly doped shallow junctions with improved activation have been widely investigated in recent CMOS technologies. In this scope, sub-melt millisecond laser annealing has been introduced in
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::86bbf2f4fd0f139346b065422fbb566a
https://doi.org/10.1016/j.tsf.2009.09.151
https://doi.org/10.1016/j.tsf.2009.09.151
Autor:
J.C. Dupuy, G. Bryce, Nicolas Gaillard, S. Chhun, J. Vitiello, V. Girault, M. Hopstaken, J. Guillan, Joaquim Torres, L.G. Gosset, B. Van Schravendijk, J. Michelon, Pascal Bancken, S. Courtas, R. Gras, Marc Juhel, L. Pinzelli, C. Debauche
Publikováno v:
Microelectronic Engineering. 83:2094-2100
Self-aligned barriers are widely investigated either in replacement of dielectric liners to decrease the total interconnect k value or as a treatment prior standard dielectric barrier deposition to improve reliability performances. In this paper, a t
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::a69f8a8c59131b6a249c8aad8379dfdd
https://doi.org/10.1016/j.mee.2006.09.013
https://doi.org/10.1016/j.mee.2006.09.013
Autor:
Alexis Farcy, Philippe Delpech, Francois Leverd, Lucile Broussous, Sebastien Cremer, Remi Beneyton, Nathalie Vulliet, Ali Ayazi, Lieven Verslegers, D. Pelissier-Tanon, N-K Hon, T. Quemerais, L. Salager, Cedric Durand, Subal Sahni, E. Gourvest, P. De Dobbelaere, Olivier Gourhant, J.F. Carpentier, K. Haxaire, Yannick Sanchez, M. Fourel, P. Brun, C. Richard, Attila Mekis, Frederic Boeuf, M. Guillermet, D. Benoit, L. Pinzelli, Peng Sun, Y. Le-Friec, B. Sautreuil, Y. Chi, F. Battegay, B. Orlando, F. Baron, Daniel Gloria, E. Batail, Thierry Pinguet, D. Monnier, H. Petiton, D. Ristoiu, Jean-Robert Manouvrier, Gianlorenzo Masini, Sébastien Jan
Publikováno v:
2013 IEEE International Electron Devices Meeting.
Recently Silicon Photonics has generated an outstanding interest for integrated optical communications. In this paper we describe a 300mm Silicon Photonics platform designed for 25Gb/s and above applications at the three typical communication wavelen
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::a960f0db21112f5d1e743e8e26cef219
https://doi.org/10.1109/iedm.2013.6724623
https://doi.org/10.1109/iedm.2013.6724623
Autor:
M. Mellier, Michel Haond, D. Barge, Dominique Golanski, E. Richard, Franck Arnaud, N. Guillot, Nicolas Planes, David Petit, P. Perreau, L. Pinzelli, Y. Campidelli, C. Fenouillet-Beranger, S. Lagrasta, Olivier Weber, B. Dumont, V. Barral, Pascal Gouraud
Publikováno v:
2013 International Symposium on VLSI Technology, Systems and Application (VLSI-TSA).
This work highlights the way to optimize the speed/power performance of the planar FDSOI technology at the 28nm node and beyond. The combination of gate length shrink and spacerO increase leads to 13% delay decrease and 15% dynamic power saving at sa
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::12cd83c92236594dc2a84e48e3fa020e
https://doi.org/10.1109/vlsi-tsa.2013.6545645
https://doi.org/10.1109/vlsi-tsa.2013.6545645
Autor:
P. Perreau, C. Fenouillet-Beranger, Frederic Boeuf, C. Perrot, Sébastien Barnola, C. de Buttet, F. Boedt, Konstantin Bourdelle, O. Faynot, Olivier Weber, Francois Andrieu, F. Abbate, Tomasz Skotnicki, S. Peru, L. Pinzelli, Thierry Poiroux, Pascal Gouraud, P. Boulenc, Y. Campidelli, L. Tosti, Remi Beneyton, A. Margain, Bich-Yen Nguyen
Publikováno v:
2011 Proceedings of the European Solid-State Device Research Conference (ESSDERC).
In this paper we explore the impact of the parasitic bipolar in undoped channel Ultra-Thin BOX (UTBOX) with and without Ground Plane (GP) on a 32 nm Fully-Depleted SOI (FDSOI) high-k/metal gate technology. The static parasitic bipolar latch occurs at
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_dedup___::fb4c010aab7814a296036ee1e69c503a
https://doi.org/10.1109/essderc.2011.6044222
https://doi.org/10.1109/essderc.2011.6044222