Zobrazeno 1 - 10
of 188
pro vyhledávání: '"L. Pantisano"'
Publikováno v:
2022 IEEE International Reliability Physics Symposium (IRPS).
Autor:
B. Moser, Matthew W. Stoker, L. Pantisano, J. B. Johnson, M. Zhao, L. Jang, Dina H. Triyoso, K. D. Seo, E. Kaganer, J. Freeman, U. Rana, S. Raman, R. Krishnan, A. Reznicek, David P. Brunco
Publikováno v:
DRC
For the first time, we present a Super Steep Retrograde Well (SSRW) FinFET process utilizing patterned well implants and Si-based epitaxy channels and compare to a state-of-the-art production technology (14LPP) [1]. This flow offers simpler integrati
Autor:
Jorge A. Kittl, Ludovic Goux, S. Cimino, C. Adelmann, Dirk Wouters, Malgorzata Jurczak, Valery V. Afanas'ev, L. Pantisano, Y. Y. Chen
Publikováno v:
Microelectronic Engineering. 88:1251-1254
The band alignment between a dielectric and a metal gate is crucial as it controls the MOSFET threshold voltage as well as the leakage in metal-insulator-metal (MIM) structure. In the ideal Schottky-Mott model the barrier height should be controlled
Autor:
Joonmyoung Lee, Jungho Shin, Jubong Park, Byung-Hun Lee, S. Cimino, Seungjae Jung, Sangsu Park, Myungwoo Son, Hyunsang Hwang, Wootae Lee, Seonghyun Kim, L. Pantisano
Publikováno v:
IEEE Electron Device Letters. 32:1665-1667
We proposed a Mo/SiOx/Pt resistive random access memory (RRAM) device as an alternative to static random access memory (SRAM) devices for field-programmable gate array (FPGA) applications. In order to evaluate the feasibility of our RRAM device for F
Publikováno v:
Microelectronics Reliability. 40:1347-1352
A novel plasma-process induced damage depassivation method is proposed. Using a staircase-like stress voltage and varying the stress time, we were able to depassivate the latent damage at very low-field on both nMOS and pMOS devices. The dynamic of t
Autor:
G. Valentini, S. Alba, L. Pettarin, L. Baldi, A. Scarpa, Alessandro Paccagnella, L. Pantisano
Publikováno v:
Microelectronics Reliability. 38:919-924
Plasma processing has become an integral part of the IC fabrication, since it offers advantages in terms of directionality, low temperature and process convenience. However plasma processing induces an oxide charging damage, which is function of proc
Autor:
L. Pantisano, L. Trojman, S. Severi, E.San Andres, C. Kerner, A. Veloso, I. Ferain, T. Hoffman, G. Groeseneken, S. de Gendt
Publikováno v:
2007 International Symposium on VLSI Technology, Systems and Applications (VLSI-TSA)
2007 International Symposium on VLSI Technology, Systems and Applications (VLSI-TSA), Apr 2007, Hsinchu, Japan. pp.1-2, ⟨10.1109/VTSA.2007.378909⟩
2007 International Symposium on VLSI Technology, Systems and Applications (VLSI-TSA), Apr 2007, Hsinchu, Japan. pp.1-2, ⟨10.1109/VTSA.2007.378909⟩
An original detailed methodology has been demonstrated for comparing short channel device performances in HfSiON and two different MG integration schemes. In HfSiON there is substantial room for improvement towards shorter metallurgical gate length a
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_dedup___::da75c9db7f3fdce999bf295b6431a47a
https://hal.archives-ouvertes.fr/hal-02952258
https://hal.archives-ouvertes.fr/hal-02952258
Autor:
Guido Groeseneken, Eduard A. Cartier, Y. Manabe, Matty Caymax, S. E. Jang, A. Kerber, G. Lujan, Marc Heyns, Chao Zhao, Thierry Conard, S. Lin, J.D. Chen, Vidya Kaushik, Hugo Bender, E. Young, Wilfried Vandervorst, Robin Degraeve, J. Kluth, L. Pantisano, V. Cosnier, Wilman Tsai, S. Van Elshocht, E. Rohr, S. De Gendt, Richard Carter, S. Kubicek, J. Pétry
Publikováno v:
Frontiers in Electronics.
Once the thickness of the gate dielectric layer in CMOS devices gets thinner than 1.2 nm, excessive gate leakage due to direct tunneling makes the use of alternative materials obligatory. Candidate high-k materials are metal oxides such as Al 2 O 3,
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Conference
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