Zobrazeno 1 - 10 of 20 pro vyhledávání: '"L. Gaben"'
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Hydrogen silsesquioxane tri-dimensional advanced patterning concepts for high density of integration in sub-7 nm nodes
Autor: B. Hemard, Sébastien Barnola, L. Gaben, S. Pauliac, Virginie Loup, C. Euvrard, J.-A. Dallery, Y. Exbrayat, M.-P. Samson, Thomas Skotnicki, Christian Arvet, M. Vinet, X. Bossy, C. Vizioz, L. Koscianski, Frederic Boeuf, C. Perrot, R. Dechanoz, J. Bustos, B. Previtali, B. Perrin, V. Balan, Francis Balestra, James C. Sturm, S. Barraud, Stephane Monfray, Pascal Besson
Publikováno v: 2017 EUROSOI-ULIS Proceedings
2017 Joint International EUROSOI Workshop and International Conference on Ultimate Integration on Silicon (EUROSOI-ULIS)
2017 Joint International EUROSOI Workshop and International Conference on Ultimate Integration on Silicon (EUROSOI-ULIS), Apr 2017, Athens, Greece. pp.120-123, ⟨10.1109/ULIS.2017.7962617⟩
Best paper award; session 9: Novel Materials and Technologies; International audience; Recent developments in CMOS devices such as FinFET, FDSOI or stacked nanowire FETs (SNWFETs) have led the industry to consider increasingly complex integration pro
Externí odkaz: https://explore.openaire.eu/search/publication?articleId=doi_dedup___::ca7595340398bf8248e822cfce7e8ba8
https://hal.archives-ouvertes.fr/hal-02014232
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3
Vertically Stacked-NanoWires MOSFETs in a Replacement Metal Gate Process with Inner Spacer and SiGe Source/Drain
Autor: N. Rambal, I. Tinti, Zineb Saghi, V. Balan, O. Faynot, G. Audoit, Nicolas Bernier, F. Allain, Christian Arvet, Claude Tabone, Nicolas Posseme, B. Previtalli, Sylvain Barraud, C. Vizioz, J.M. Hartmann, A. Toffoli, E. Augendre, C. Euvrard, L. Gaben, Yves Morand, Patricia Pimenta-Barros, C. Comboroure, V. Lapras, R. Coquand, V. Maffini-Alvaro, Shay Reboh, David Cooper, Laurent Grenouillet, M.-P. Samson, J. Daranlot, Olivier Rozeau, Maud Vinet, Virginie Loup
Publikováno v: 2016 IEEE International Electron Devices Meeting (IEDM)
2016 IEEE International Electron Devices Meeting (IEDM), Dec 2016, San Francisco, United States. ⟨10.1109/IEDM.2016.7838441⟩
International audience; We report on vertically stacked horizontal Si NanoWires (NW) p-MOSFETs fabricated with a replacement metal gate (RMG) process. For the first time, stacked-NWs transistors are integrated with inner spacers and SiGe source-drain
Externí odkaz: https://explore.openaire.eu/search/publication?articleId=doi_dedup___::29412b777acc4388dc0419b37ccb3235
https://hal-cea.archives-ouvertes.fr/cea-01973383/document
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5
HSQ Lithography for Nanowire First Integration: an Interesting Alternative for Gate Last Fabrication of Sub-7nm Stacked Nanowire FETs
Autor: Thomas Skotnicki, L. Koscianski, M.-P. Samson, S. Pauliac, M. Vinet, J. Bustos, Stephane Monfray, J.-A. Dallery, Frederic Boeuf, Francis Balestra, X. Bossy, L. Gaben, R. Dechanoz, S. Barraud, B. Hemard
Publikováno v: Book of Abstracts of the 2016 SSDM
2016 International Conference on Solid State Devices and Materials
2016 International Conference on Solid State Devices and Materials, Sep 2016, Tsukuba, Japan. pp.O-3-03 FinFET and Nanowire FET
International audience
Externí odkaz: https://explore.openaire.eu/search/publication?articleId=doi_dedup___::4667bf7f5eabe603978df3f1fb87c46a
https://hal.archives-ouvertes.fr/hal-02015707
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6
Stacked Nanowires FETs: Mechanical robustness evaluation for sub-7nm nodes
Autor: Francis Balestra, Frederic Boeuf, Arthur Arnaud, L. Gaben, Thomas Skotnicki, C. Vizioz, Stephane Monfray, J.M. Hartmann, Marios Barlas, S. Barraud, Christian Arvet, M.-P. Samson, M. Vinet
Publikováno v: 2016 SNW proceedings
2016 Silicon Nanoelectronics Workshop (SNW)
2016 Silicon Nanoelectronics Workshop (SNW), Jun 2016, Honolulu, United States. pp.136-137, ⟨10.1109/SNW.2016.7578020⟩
session 8: advanced CMOS and New Devices Concepts; International audience; Stacked Nanowires FETs are proposed to replace FinFET and FDSOI for sub-7nm nodes. While most studies demonstrate the performances gain offered by such structures, mechanical
Externí odkaz: https://explore.openaire.eu/search/publication?articleId=doi_dedup___::16aa40395878f75fd766f16ed3c332bc
https://doi.org/10.1109/snw.2016.7578020
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7
(Invited) Evaluation of Stacked Nanowires Transistors for CMOS: Performance and Technology Opportunities
Autor: Maud Vinet, Thomas Skotnicki, C. Vizioz, Catherine Euvrard-Colnat, Christian Arvet, Stephane Monfray, L. Gaben, Sebastien Pauliac, Jessy Bustos, F. Boeuf, Jacques-Alexandre Dallery, Marie-Pierre Samson, Joris Lacord, Jean-Michel Hartmann, Francis Balestra, Viorel Balan, Olivier Rozeau, Virginie Loup, Pascal Besson, Marie-Anne Jaud, S. Barraud, Sebastien Martinie, Cédric Perrot
Publikováno v: 229th ECS Meeting: 6th Symposium on Silicon Compatible Materials, Processes, and Technologies for Advanced Integrated Circuits and Emerging Applications
229th ECS Meeting: 6th Symposium on Silicon Compatible Materials, Processes, and Technologies for Advanced Integrated Circuits and Emerging Applications, F. Roozeboom, P.J. Timans, E.P. Gusev, V. Narayanan, K. Kakushima, Z. Karim, S. De Gendt, May 2016, San Diego, United States
ECS Transactions
ECS Transactions, Electrochemical Society, Inc., 2016, 72 (4), pp.43-54. ⟨10.1149/07204.0043ecst⟩
ECS Transactions, 2016, 72 (4), pp.43-54. ⟨10.1149/07204.0043ecst⟩
Due to the unavoidable short channel effects associated with planar bulk silicon MOSFET scaling, FinFET and FDSOI have become the most used solutions for the latest generations of CMOS. Gate control over the channel is excellent and performances are
Externí odkaz: https://explore.openaire.eu/search/publication?articleId=doi_dedup___::deb27c2bb21091188fa39d9bc2d9ebf7
https://hal.archives-ouvertes.fr/hal-02014098
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8
Ω-Gate Nanowire Transistors Realized by Sidewall Image Transfer Patterning: 35nm Channel Pitch and Opportunities for Stacked-Nanowires Architectures
Autor: Frederic Boeuf, S. Barraud, F. Balestra, F. Alain, T. Skotnicki, B. Previtali, P. Besson, S. Monfray, J. Pradelles, P. Pimenta-Barros, M Vinet, Yves Morand, M.-P. Samson, L. Gaben
Publikováno v: Book of abstracts of the 2015 SSDM
2015 international Conference on Solid State Devices and Materials
2015 international Conference on Solid State Devices and Materials, Sep 2015, Sapporo, Japan. N-2-2 Process for fully depleted devices
SSDM Young Researcher Award; International audience
Externí odkaz: https://explore.openaire.eu/search/publication?articleId=doi_dedup___::c96ac4452a400e8a8d408a6225225575
https://hal.archives-ouvertes.fr/hal-02015323
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9
Opportunities and challenges of nanowire-based CMOS technologies
Autor: M.-P. Samson, M. Casse, O. Rozeau, L. Gaben, M. Vinet, J. Laccord, F. Glowacki, N. Bernier, Sebastien Martinie, B. De Salvo, V. Maffini-Alvaro, F. Allain, P. Pimenta-Barros, S. Barraud, Phuong Nguyen, J.M. Hartmann, Marie-Anne Jaud, C. Vizioz, Claude Tabone, Christian Arvet
Publikováno v: 2015 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference (S3S).
The Nano Wire (NW) CMOS technology is widely considered as a promising evolutionary solution of current FinFET technology. The main advantage of the nanowire transistors for ultimate CMOS scaling is their optimal electrostatic confinement. In this pa
Externí odkaz: https://explore.openaire.eu/search/publication?articleId=doi_________::e6ac522b46a981dd8e7da70d460de759
https://doi.org/10.1109/s3s.2015.7333520
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