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pro vyhledávání: '"L. Desvoivres"'
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Autor:
R. Ranica, R. Berthelon, A. Gandolfo, G. Samanni, E. Gomiero, J. Jasse, P. Mattavelli, J. Sandrini, M. Querre, Y. Le-Friec, J. Poulet, V. Caubet, L. Favennec, C. Boccaccio, G. Ghezzi, C. Gallon, JC. Grenier, B. Dumont, O. Weber, A. Villaret, R. Beneyton, N. Cherault, D. Ristoiu, S. Del Medico, O. Kermarrec, JP. Reynard, P. Boivin, A. Souhaite, L. Desvoivres, S. Chouteau, PO. Sassoulas, L. Clement, A. Valery, E. Petroni, D. Turgis, A. Lippiello, L. Scotti, F. Disegni, A. Ventre, D. Ornaghi, M. De Tomasi, A. Maurelli, A. Conte, F. Arnaud, A. Redaelli, R. Annunziata, P. Cappelletti, F. Piazza, P. Ferreira, R. Gonella, E. Ciantar
Publikováno v:
2021 IEEE International Electron Devices Meeting (IEDM).
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::652fcb15ec770ffda0355c498b7b0e9e
https://doi.org/10.1109/iedm19574.2021.9720669
https://doi.org/10.1109/iedm19574.2021.9720669
High Density Embedded PCM Cell in 28nm FDSOI Technology for Automotive Micro-Controller Applications
Autor:
Roberto Annunziata, L. Favennec, F. Disegni, D. Turgis, Jean-Luc Ogier, Remi Beneyton, Xavier Federspiel, N. Cherault, Fausto Piazza, A. Gandolfo, M. Molgg, E. Ciantar, Enrico Gomiero, P.O. Sassoulas, J. P. Reynard, B. Dumont, S. Delmedico, Alexandre Villaret, Olivier Weber, A. Viscuso, Franck Arnaud, L. Clement, L. Desvoivres, Paulo Ferreira, Paolo Mattavelli, C. Gallon, R. Ranica, O. Kermarrec, J. Jasse, S. Chouteau, C. Jahan, C. Boccaccio, Paolo Cappelletti, A. Souhaite, G. Samanni, Paola Zuliani, R. Berthelon, V. Caubet, Philippe Boivin, D. Ristoiu, Alfonso Maurelli, J. C. Grenier
Publikováno v:
2020 IEEE International Electron Devices Meeting (IEDM).
in this paper we present an enhancement of our 28nm FDSOI-PCM solution using Bipolar Junction Transistor (BJT) selector co-integrated with triple gate oxide devices scheme (logic/1,8V/5V) for advanced automotive microcontroller designs. Leveraging FD
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::cb9d7d45a06fe3730a77e9eea337f87a
https://doi.org/10.1109/iedm13553.2020.9371934
https://doi.org/10.1109/iedm13553.2020.9371934
Autor:
J. Micout, M. Casse, J.-P. Colinge, L. Desvoivres, Vincent Delaye, C. Fenouillet-Beranger, S. Barraud, X. Garros, Perrine Batude, J.M. Hartmann, R. Bortolin, V. Mazzocchi, Frédéric Mazen, G. Romano, B. Mathieu, N. Rambal, V. Balan, Zineb Saghi, F. Allain, M.-P. Samson, P. Besombes, C. Comboroure, M. Vinet, Quentin Rafhay, Joris Lacord, Claude Tabone, Alain Toffoli, Gerard Ghibaudo, C. Vizioz, Benoit Sklenard, V. Lapras, L. Lachal, Laurent Brunet, Virginie Loup
Publikováno v:
2017 IEDM Technical Digest
2017 IEEE International Electron Devices Meeting (IEDM)
2017 IEEE International Electron Devices Meeting (IEDM), Dec 2017, San Francisco, United States. pp.32.2.1-32.2.4, ⟨10.1109/IEDM.2017.8268484⟩
2017 IEEE International Electron Devices Meeting (IEDM)
2017 IEEE International Electron Devices Meeting (IEDM), Dec 2017, San Francisco, United States. pp.32.2.1-32.2.4, ⟨10.1109/IEDM.2017.8268484⟩
session 32: Process and Manufacturing Technology (32.2); International audience; For the first time, a low temperature (LT) FinFET process is demonstrated, using Solid Phase Epitaxy Regrowth (SPER), gate last integration and Self Aligned Contact (SAC
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_dedup___::f667185abf93ecbc97dd4a441fb34f4d
https://hal.archives-ouvertes.fr/hal-01959097
https://hal.archives-ouvertes.fr/hal-01959097
Publikováno v:
Microelectronic Engineering. 84:2109-2112
Plasma processes used for strip resist and etch oxide in CMOS technologies may degrade the quality of the silicon surface if it is protected of the plasma by a too thin oxide capping. Using AFM measurements, we have identified this degradation as a s
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::7c8673f0a5efaebe72739e6a5fe402c6
https://doi.org/10.1016/j.mee.2007.04.072
https://doi.org/10.1016/j.mee.2007.04.072
Publikováno v:
SPIE Proceedings.
Planar Fully-Depleted (FD) Silicon On Insulator (SOI) MOSFET technology has already demonstrated large performance boost vs bulk at 28nm node (>30%) and is very competitive for incoming mobile & multimedia products thanks to design porting from bulk.
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::f0ffaeb91e539dfad2348c328349d22b
https://doi.org/10.1117/12.2045904
https://doi.org/10.1117/12.2045904
Autor:
L. Desvoivres, Maxime Argoud, Raluca Tiron, Ahmed Gharbi, Jonathan Pradelles, Nicolas Posseme, Sylvain Barraud, Christian Arvet, Sébastien Barnola, C. Vizioz, P. Pimenta Barros
Publikováno v:
SPIE Proceedings.
For 11nm and below, several alternatives are still potential candidates to meet the patterning requirements. Spacer patterning, Mask Less Lithography (i.e. Electron beam lithography) and Direct Self Assembly are alternatives under development at CEA-
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::5888440ac82051aed662c07149365545
https://doi.org/10.1117/12.2046251
https://doi.org/10.1117/12.2046251
Publikováno v:
Microelectronic Engineering. 46:295-298
When optimizing a 0.1 μm gate etching process using a standard chemistry and plasma operating conditions, we have observed an unsuspected behavior of thin gate oxides. By combining X-ray Photoelectron Spectroscopy (XPS) and spectroscopic ellipsometr
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::a4f1cfafa5e4f55a8c2e61d56ded369e
https://doi.org/10.1016/s0167-9317(99)00085-4
https://doi.org/10.1016/s0167-9317(99)00085-4
Autor:
X. Garros, P. Caubet, L. Tosti, Francois Andrieu, N. Allouti, C. Le Royer, F. Ponthenier, Sébastien Barnola, P.K. Baumann, S. Morvan, U. Weber, P. Perreau, Gerard Ghibaudo, A. Seignard, C. Euvrard, Yves Morand, Maurice Rivoire, L. Desvoivres, M.-C. Roure, C. Leroux, F. Martin, R. Gassilloud, M. Casse, Olivier Weber, Thierry Poiroux, Pascal Besson
Publikováno v:
Microelectronic Engineering
Microelectronic Engineering, Elsevier, 2013, 109, pp.306-309. ⟨10.1016/j.mee.2013.03.045⟩
Microelectronic Engineering, 2013, 109, pp.306-309. ⟨10.1016/j.mee.2013.03.045⟩
Microelectronic Engineering, Elsevier, 2013, 109, pp.306-309. ⟨10.1016/j.mee.2013.03.045⟩
Microelectronic Engineering, 2013, 109, pp.306-309. ⟨10.1016/j.mee.2013.03.045⟩
Graphical abstractDisplay Omitted We integrated a gate-last on high-k first on planar fully depleted SOI MOSFETs.pMOSFETs reach a low threshold voltage of VTp=-0.2V.Gate-last pMOSFETS present one decade gate current gain compared to gate first ones.T
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_dedup___::55f688bcbb398063cfd6caffbf58fdf0
https://hal.archives-ouvertes.fr/hal-00996453
https://hal.archives-ouvertes.fr/hal-00996453
Publikováno v:
SPIE Proceedings.
Gate patterning control for 28nm Fully Depleted Silicon On Insulator (FD-SOI) technology faces several challenges. For lithography and etch , usage of DoseMapper requires extensive and accurate metrology to compute adequate dose recipes. From etch si
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::3e512f726a60ae9768fd42368b526ff3
https://doi.org/10.1117/12.2010746
https://doi.org/10.1117/12.2010746