Zobrazeno 1 - 10
of 23
pro vyhledávání: '"L. D. Cheremisinova"'
Publikováno v:
Informatika, Vol 21, Iss 3, Pp 23-38 (2024)
Objectives. The problem of restoring the functional description of digital VLSI devices presented at the transistor level is considered. The objective of the work is to develop means for extraction of blocks representing logical networks from two-lev
Externí odkaz:
https://doaj.org/article/32448e099ee5418292a2e621d403fbf2
Publikováno v:
Informatika, Vol 20, Iss 4, Pp 24-37 (2023)
Objectives. The problem of functional verification of control devices with respect to their design specification is considered. When solving the problems of implementing and testing of discrete systems, one has to deal with the presence of parallelis
Externí odkaz:
https://doaj.org/article/c2e002bc148a4accbc1c4c22c549a35d
Publikováno v:
Informatika, Vol 19, Iss 3, Pp 25-39 (2022)
Objectives. The objective of the work is to develop the means for recognition (extraction) of high-level structures in circuits on transistor level. This allows to obtain a representation on logical level, equivalent to original flat description on t
Externí odkaz:
https://doaj.org/article/f3e241cb3ad5411a9ad2b973a013993e
Publikováno v:
Informatika, Vol 18, Iss 4, Pp 96-107 (2021)
O b j e c t i v e s. With the increasing complexity of verification and simulation of modern VLSI, containing hundreds of millions of transistors, the means of extracting the hierarchical description at the level of logical elements froma flat descri
Externí odkaz:
https://doaj.org/article/caebc33c9a334e5ba346be8f41a13e0c
Publikováno v:
Informatika, Vol 16, Iss 2, Pp 62-72 (2019)
Considered problem of model based verification of control systems is the checking whether the system behavior satisfies the requirements fixed in the design specification The testing includes the experiments consisting in simulation of investigated s
Externí odkaz:
https://doaj.org/article/52ef6c5acb0a465e966d1fecb59e4c4b
Autor:
L. D. Cheremisinova
Publikováno v:
Informatika, Vol 0, Iss 4(56), Pp 104-110 (2017)
The article reflects the problem of the average power estimation which is consumed by a CMOS circuit by means of its simulation on the test sequence of input actions. The method of forming test sequences of complete enumeration for sequential circuit
Externí odkaz:
https://doaj.org/article/394739da956143c6b2e70127f5698922
Publikováno v:
Informatika, Vol 0, Iss 1(53), Pp 112-124 (2017)
Arkadij Dmitrievich Zakrevskij was at the beginnings of cybernetics origin in the Soviet Union. He is the founder of one of the known schools of logical design in the Soviet Union and all the world. This paper is devoted to the science heritage of A.
Externí odkaz:
https://doaj.org/article/fa766bb5a30c48868b04354d1ddcf9ff
Publikováno v:
Informatika, Vol 0, Iss 4, Pp 82-93 (2016)
A problem of synthesis of multi-level logical networks using CMOS VLSI cell library is considered. The networks are optimized with respect to the die size and average dissipated power by CMOS-circuit implemented on a VLSI chip. The suggested approach
Externí odkaz:
https://doaj.org/article/8d1c4d3d64034f4d9fc080e90ea10cf9
Autor:
N. A. Kirienko, L. D. Cheremisinova
Publikováno v:
Informatika, Vol 0, Iss 3, Pp 59-66 (2016)
The influence of procedures of technology independent optimization of functional descriptions on complexity and delay of circuits made of CMOS VLSI library elements is investigated. The effectiveness of the optimization methods implemented in the syn
Externí odkaz:
https://doaj.org/article/a6ba623f727047d19b0dfe1a22354320
Autor:
L. D. Cheremisinova
Publikováno v:
Informatika, Vol 0, Iss 1, Pp 80-89 (2016)
The problem under consideration is to reduce the area of the layout of regular VLSI structures by means of their multiple folding. The method of solving the key problem of multiple folding, which is implementability checking of the folding set, is su
Externí odkaz:
https://doaj.org/article/c56323a477bd41e0b78e456e137cb469