Zobrazeno 1 - 10
of 12
pro vyhledávání: '"Kyung-Tae Do"'
Publikováno v:
IEEE Transactions on Very Large Scale Integration (VLSI) Systems. 26:37-49
As the semiconductor process technology continuously scales down, circuit delay variations due to manufacturing and environmental variations become more and more serious. These delay variations are hardly predictable and thus require an additional de
Publikováno v:
DATE
As process technology scales down, circuit delay variations become more and more serious due to manufacturing and environmental variations. The delay variations are hardly predictable and thus require additional design margin and impede the chance to
Autor:
Abhishek Mittal, Abhishek Ranjan, Jung Yun Choi, Jianfeng Liu, Kyung-Tae Do, Mohit Kumar, Nikhil Tripathi, Raj Shekhar, Srihari Yechangunja, Minyoung Mo, SungHo Park
Publikováno v:
DATE
Resets are required in the design to initialize the hardware for system operation and to force it into a known state for simulation or to recover from an error. Given the increasing design complexity and time-to-market pressures, figuring out the reg
Publikováno v:
IEEE Transactions on Very Large Scale Integration (VLSI) Systems. 18:602-615
This paper presents a novel method for full-chip statistical leakage estimation that considers the impact of process variation. The proposed method considers the correlations among leakage currents in a chip and the state dependence of the leakage cu
Publikováno v:
Integration. 40:62-73
We present a new timing model for latch-controlled sub-systems, referred to as the advanced black box model. The proposed model considers the transparency characteristics of latches in modeling and uses only the constraints on input signals and the c
Autor:
Jung Yun Choi, Bernd Becker, Kee Sup Kim, Kyung-Tae Do, Young Moon Kim, Hyung-Ock Kim, Matthias Sauer, Jun Seomun, Subhasish Mitra
Publikováno v:
CICC
Using 28nm test chips, we derive signatures for early-life failures (ELF) in both high-K/metal-gate transistors and ultra low-K inter-metal dielectrics. We also demonstrate that the derived ELF signatures can be successfully detected using a clock co
Autor:
Jung Yun Choi, Bernd Becker, Young Moon Kim, Kyung-Tae Do, Matthias Sauer, Subhasish Mitra, Jun Seomun, Kee Sup Kim, Hyung-Ock Kim
Publikováno v:
ITC
Early-life failures (ELF) result from weak chips that may pass manufacturing tests but fail early in the field, much earlier than expected product lifetime. Recent experimental studies over a range of technologies have demonstrated that ELF defects r
Autor:
Jun Seomun, Chungki Oh, Kee Sup Kim, Wook Kim, Hyo-sig Won, Jae-Han Jeon, Kyung-Tae Do, Hyung-Ock Kim
Publikováno v:
ISOCC
Thermal management, which dynamically throttles frequency and voltage, is de facto standard in high performance mobile SoC to sustain device surface temperature under specific level; and throttling must accompany with computation slowdown. To minimiz
Publikováno v:
2008 5th International Conference on Electrical Engineering/Electronics, Computer, Telecommunications and Information Technology.
This paper compares characteristics and performances of characterization methods for statistical timing analysis and statistical leakage estimation. Two popular characterization methods, regular grid sampling and distribution based sampling are selec
Publikováno v:
2009 International SoC Design Conference (ISOCC); 2009, p45-48, 4p