Zobrazeno 1 - 10
of 18
pro vyhledávání: '"Kyung-Sub Son"'
Publikováno v:
IEEE Transactions on Circuits and Systems II: Express Briefs. 67:974-978
A 0.42 to 3.45 Gb/s counter-based referenceless clock and data recovery (CDR) circuit that has an unrestricted and continuous-rate frequency acquisition capability is presented. The proposed frequency detector first selects a frequency driving direct
Publikováno v:
IEEE Transactions on Circuits and Systems I: Regular Papers. 66:2907-2920
This paper describes a low-power reference-less 5.4-Gb/s clock and data recovery (CDR) circuit with a fully digital quarter-rate linear phase detector (QLPD) having an extended pulse width output. By using a fully digital circuit and merging XOR func
Publikováno v:
2019 International SoC Design Conference (ISOCC).
— An eye-open monitoring system based on signal counting is introduced. Data is sampled 2048 times and "0" or "1" is counted to determine eye-opening at each sampling point. The FPGA stores the counter value and outputs the estimated eye-diagram. T
Publikováno v:
ISOCC
A two-step time-to-digital converter using a ring oscillator time amplifier is presented. The time amplifier structure does not accumulates the error in the iterative process of time. There are 8 bits in total, of which 4 bits are obtained in the coa
Publikováno v:
APCCAS
This paper presents a burst-mode clock and data recovery (CDR) circuit based on two symmetric VCO's. Compared with the conventional structure with a T/2 delay cell based approach, the proposed structure shows the better re timing margin without any d
Publikováno v:
ISOCC
Thispaper presents a 200-Mb/s to 3-Gb/s half-rate referenceless clock and data recovery (CDR) circuit in 180nm CMOS process. A bidirectional frequency detector (FD) is proposed to eliminate the harmonic locking issue and reduce the frequency acquisit
Publikováno v:
IEICE Electronics Express. 16:20181064-20181064
Publikováno v:
IEICE Electronics Express. 16:20190601-20190601
Publikováno v:
ISCAS
We propose an on-chip circuit technique to characterize jitter tolerance of binary clock and data recovery (CDR) circuit. The proposed jitter modulation scheme incorporates modulating-charge-pump and pulse-generator circuits to apply a periodic trian
Publikováno v:
2014 International SoC Design Conference (ISOCC).
This paper presents an auto-delay offset cancellation technique for time difference repeating amplifier. Pipeline time-to-digital converter (TDC) achieves fine resolution by amplifying the time residue. Therefore the linearity of the time difference