Zobrazeno 1 - 10
of 42
pro vyhledávání: '"Kyung-Soo Ha"'
Autor:
Hyong-Ryol Hwang, Young-Soo Sohn, Young Hoon Son, Seungseob Lee, Seung-Jun Bae, Hyuck-Joon Kwon, Jung-Bae Lee, Byongwook Na, Chang-Kyo Lee, Young-Hwa Kim, Dongkeon Lee, Duk-ha Park, Daesik Moon, Kwang-Il Park, Tae-Young Oh, Youn-sik Park, Kyung-Soo Ha
Publikováno v:
IEEE Journal of Solid-State Circuits. 55:157-166
A 7.5 Gb/s/pin 8-Gb LPDDR5 SDRAM is implemented in a 1 $\times$ nm DRAM process. Various techniques are applied to achieve higher bandwidth and lower power than LPDDR4X. To increase data rate, a WCK clocking scheme that is less vulnerable to power no
Autor:
Jongwook Park, Jung-Hwan Choi, Seung-Jun Bae, Si-Hyeong Cho, Seunseob Lee, Young-Ryeol Choi, In-Dal Song, Kwang-Il Park, Ki-Ho Kim, Jin-Seok Heo, Young-Soo Sohn, Dong-Hun Lee, Eunsung Seo, Junha Lee, Gil-Hoon Cha, Hyuck-Joon Kwon, Jin-Hyeok Baek, Daesik Moon, Youn-sik Park, Kyung-Soo Ha, Chang-Kyo Lee, Seok-Hun Hyun, Seong-Jin Jang
Publikováno v:
IEEE Journal of Solid-State Circuits. 53:2906-2916
This paper presents a dual-loop two-step ZQ calibration scheme with a 20-nm DRAM process to support dedicated supply voltages ( $V_{DD}$ and $V_{DDQ}$ ). The proposed calibration scheme improves system signal integrity by maintaining the targeted out
Autor:
Soo-bong Chang, Young-Soo Sohn, Hyuck-Joon Kwon, Duk-ha Park, Hyong-Ryol Hwang, Junghwan Park, Kwang-II Park, Choi Yeon-Kyu, Young Hoon Son, Hyunyoon Cho, Byongwook Na, Hyung-Joon Chi, Lim Suk-Hyun, Jin-Hun Jang, Tae-Young Oh, Seung-Jun Shin, Seouk-Kyu Choi, Daesik Moon, Kim Sang-Yun, Ki-Won Park, Seong-Jin Jang, Hyo-Joo Ahn, Jung-Hwan Choi, Seungseob Lee, Chang-Kyo Lee, Dongkeon Lee, Young-Hwa Kim, Youn-sik Park, Kyung-Soo Ha, Seok-Hun Hyun
Publikováno v:
ISSCC
High-speed and low-power techniques for the latest mobile DRAMs, such as LPDDR4/4X [1–3], have been developed to enable high-resolution displays, multiple cameras and 4G communication in mobile devices. However, DRAM with higher bandwidth and lower
Publikováno v:
IEEE Transactions on Circuits and Systems I: Regular Papers. 62:2495-2503
This paper presents a forwarded-clock receiver using a mixing cell integrated injection-locked oscillator (MIILO) and an I/Q generator based on injection-locked oscillator (IQGILO). By using MIILO, jitter tolerance is enhanced by about 1.8 times at h
Autor:
Seung-Jun Bae, Jongwook Park, Young-Soo Sohn, Taesung Kim, Sewon Eom, Young-Seok Kim, Hyuck-Joon Kwon, Daesik Moon, Seong-Hwan Kim, Ki-Ho Kim, Seungseob Lee, Eungsung Seo, Jin-Hyeok Baek, Yoon-Joo Eom, Kyoung-Ho Kim, Jung-Hwan Choi, Tae-Young Oh, Gil-Hoon Cha, Seok-Hun Hyun, Yoon-Gyu Song, Youn-sik Park, Kyung-Soo Ha, Young Hoon Son, Dae-Hee Jung, In-Dal Song, Kwang-Il Park, Hyunyoon Cho, Bo-Tak Lim, Chang-Kyo Lee, Si-Hyeong Cho, Joon-Young Park, Junha Lee, Jin-Seok Heo, Young-Ryeol Choi, Seong-Jin Jang
Publikováno v:
A-SSCC
This paper presents a dual-loop 2-step ZQ calibration scheme with 20nm DRAM process to support dedicated supply voltage (VDD, VDDQ). The proposed calibration scheme maintains a target value of on-die termination (ODT) in DQ/CA regardless of the suppl
Autor:
Hye-Ran Kim, Chul-Sung Park, Kwang-Il Park, Jin-Il Lee, Young-Chul Cho, Jun-Young Park, Chang-Yong Lee, Hyoung-Joo Kim, Ki-Won Lee, Joo Sun Choi, Seong-Jin Jang, Hoe-ju Chung, Jong-ho Lee, Tae-Young Oh, Yong-Cheol Bae, Seung-Hoon Oh, Young-Ryeol Choi, Su-Yeon Doo, Kyung-Soo Ha, Tae-Seong Jang
Publikováno v:
IEEE Journal of Solid-State Circuits. 50:178-190
A 1.0 V 8 Gbit LPDDR4 SDRAM with 3.2 Gbps/pin speed and integrated ECC engine for sub-1 V DRAM core is presented. DRAM internal read-modify-write operation for data masked write makes the integrated ECC engine possible in a commodity DRAM. Time inter
Autor:
Sungwon Choi, Noh-Hun Seong, Daeseong Jung, Suyoung Sim, Jongho Woo, Nayeon Kim, Sungwoo Park, Kyung-soo Han
Publikováno v:
Atmosphere, Vol 15, Iss 2, p 218 (2024)
Specific humidity (SH) which means the amount of water vapor in 1 kg of air, is used as an indicator of energy exchange between the atmosphere and the Earth’s surface. SH is typically computed using microwave satellites. However, the spatial resolu
Externí odkaz:
https://doaj.org/article/081be2fc833e497a8119c37423c3296e
Publikováno v:
IEEE Transactions on Circuits and Systems II: Express Briefs. 61:153-157
A source synchronous architecture with constant and wide jitter-tracking bandwidth (JTB) is presented. The proposed receiver is based on an injection-locked oscillator (ILO), which provides jitter filtering and phase deskew simultaneously. While usin
An improvement of snow/cloud discrimination from machine learning using geostationary satellite data
Autor:
Donghyun Jin, Kyeong-Sang Lee, Sungwon Choi, Noh-Hun Seong, Daeseong Jung, Suyoung Sim, Jongho Woo, Uujin Jeon, Yugyeong Byeon, Kyung-Soo Han
Publikováno v:
International Journal of Digital Earth, Vol 15, Iss 1, Pp 2355-2375 (2022)
Snow and cloud discrimination is a main factor contributing to errors in satellite-based snow cover. To address the error, satellite-based snow cover performs snow reclassification tests on the cloud pixels of the cloud mask, but the error still rema
Externí odkaz:
https://doaj.org/article/a0f9836bd1124713b64f4155f600c9d7
Autor:
Hye-Yoon Joo, Seung-Jun Bae, Young-Soo Sohn, Young-Sik Kim, Kyung-Soo Ha, Min-Su Ahn, Young-Ju Kim, Yong-Jun Kim, Ju-Hwan Kim, Won-Jun Choi, Chang-Ho Shin, Soo Hwan Kim, Byeong-Cheol Kim, Seung-Bum Ko, Kwang-Il Park, Seong-Jin Jang, Gyo-Young Jin
Publikováno v:
ISSCC
A 9Gb/s/pin 8Gb GDDR5 DRAM is implemented using a 20nm CMOS process. To cover operation up to 9Gb/s, which is the highest data-rate among implemented GDDR5 DRAMs [1], this work includes an NBTI monitor, a WCK clock receiver with equalizing and duty-c