Zobrazeno 1 - 10
of 39
pro vyhledávání: '"Kyu-hyoun Kim"'
Autor:
Jinwook Oh, Alyssa Herbert, Marcel Schaal, Zhibin Ren, Ching Zhou, Siyu Koswatta, Naigang Wang, Matthew Cohen, Vidhi Zalani, Howard M. Haynie, Matthew M. Ziegler, Sae Kyu Lee, Brian W. Curran, Monodeep Kar, Martin Lutz, Xin Zhang, Robert Casatuta, Vijayalakshmi Srinivasan, Nianzheng Cao, Sunil Shukla, Pong-Fei Lu, Leland Chang, Michael A. Guillorn, Bruce M. Fleischer, Michael R. Scheuermann, Joel Abraham Silberman, Kerstin Schelm, Vinay Velji Shah, Chia-Yu Chen, Kailash Gopalakrishnan, Swagath Venkataramani, Hung Tran, Mingu Kang, Wei Wang, Jungwook Choi, Scot H. Rider, Jinwook Jung, James J. Bonanno, Radhika Jain, Li Yulong, Xiao Sun, Silvia Melitta Mueller, Kyu-hyoun Kim, Ankur Agrawal
Publikováno v:
IEEE Journal of Solid-State Circuits. 57:182-197
Reduced precision computation is a key enabling factor for energy-efficient acceleration of deep learning (DL) applications. This article presents a 7-nm four-core mixed-precision artificial intelligence (AI) chip that supports four compute precision
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::2998556a11fb9c2dbdc4775ef363b4bb
https://doi.org/10.1109/jssc.2021.3120113
https://doi.org/10.1109/jssc.2021.3120113
Autor:
Venkata Kalyan Tavva, Hillery C. Hunter, Kyu-hyoun Kim, Chitra Subramanian, M. B. Srinivas, Saravanan Sethuraman, Karthick Rajamani
Publikováno v:
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems. 39:4635-4644
Spin-transfer torque magneto-resistive random-access memory (STT-MRAM) is an exciting new emerging technology, being considered as a strong candidate to fill the gaps in the existing memory hierarchy between DRAM and the secondary memory. STT-MRAM ha
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::1232d2175ec928c45a0db318c87a270c
https://doi.org/10.1109/tcad.2020.2982134
https://doi.org/10.1109/tcad.2020.2982134
Autor:
Scot H. Rider, Martin Lutz, Moriyoshi Ohara, Pong-Fei Lu, Monodeep Kar, Xiao Sun, Kailash Gopalakrishnan, Jie Yang, Hoang Tran, Wei Wang, Michael A. Guillorn, Marcel Schaal, Ankur Agrawal, Xin Zhang, Joel Abraham Silberman, Sunil Shukla, Nianzheng Cao, James Bonano, Zhibin Ren, Sanchari Sen, Siyu Koswatta, Kyu-hyoun Kim, Mingu Kang, Swagath Venkataramani, Eri Ogawa, Vijayalakshmi Srinivasan, Hiroshi Inoue, Matt Ziegler, Howard M. Haynie, Shubham Jain, Vinay Velji Shah, Allison Allain, Jintao Zhang, Matthew Cohen, Jungwook Choi, Kerstin Schelm, Jinwook Oh, Li Yulong, Chia-Yu Chen, Ching Zhou, Naigang Wang, Jinwook Jung, Sae Kyu Lee, Silvia Melitta Mueller, Kazuaki Ishizaki, Bruce M. Fleischer, Michael R. Scheuermann, Vidhi Zalani, Brian W. Curran, Leland Chang, Mauricio J. Serrano, Ashish Ranjan, Alberto Mannari, Robert Casatuta
Publikováno v:
ISCA
The growing prevalence and computational demands of Artificial Intelligence (AI) workloads has led to widespread use of hardware accelerators in their execution. Scaling the performance of AI accelerators across generations is pivotal to their succes
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::edc72fc1439c98a561b7e0104cf8a62a
https://doi.org/10.1109/isca52012.2021.00021
https://doi.org/10.1109/isca52012.2021.00021
Autor:
Xin Zhang, Vijayalakshmi Srinivasan, Wei Wang, Jungwook Choi, Siyu Koswatta, Mingu Kang, Li Yulong, Bruce M. Fleischer, Radhika Jain, Michael R. Scheuermann, Kerstin Schelm, Kailash Gopalakrishnan, Monodeep Kar, Zhibin Ren, Michael A. Guillorn, Swagath Venkataramani, Howard M. Haynie, Xiao Sun, Matthew M. Ziegler, Hung Tran, Sae Kyu Lee, Kyu-hyoun Kim, Joel Abraham Silberman, Martin Lutz, Silvia Melitta Mueller, Sunil Shukla, Pong-Fei Lu, Vidhi Zalani, Ching Zhou, Brian W. Curran, Vinay Velji Shah, Naigang Wang, Leland Chang, Robert Casatuta, Alyssa Herbert, Nianzheng Cao, Scot H. Rider, Marcel Schaal, Ankur Agrawal, Jinwook Oh, Jinwook Jung, James J. Bonanno, Matthew Cohen, Chia-Yu Chen
Publikováno v:
ISSCC
Low-precision computation is the key enabling factor to achieve high compute densities (T0PS/W and T0PS/mm2) in AI hardware accelerators across cloud and edge platforms. However, robust deep learning (DL) model accuracy equivalent to high-precision c
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::531f331936a1c81912ee062cdc44a72e
https://doi.org/10.1109/isscc42613.2021.9365791
https://doi.org/10.1109/isscc42613.2021.9365791
Publikováno v:
ISSCC
DRAM memories continue to have a significant impact on a wide range of applications, including high-performance graphics, smartphones, server applications, and machine learning. Two 8Gb GDDR6 DRAM papers for next-generation graphics applications show
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::3b2a6a4d73712f0825cdc83d3b474973
https://doi.org/10.1109/isscc42613.2021.9365948
https://doi.org/10.1109/isscc42613.2021.9365948
Autor:
Daniel M. Dreps, Chen Qiaoli, Biao Cai, Jose A. Hejase, Junyan Tang, Stephen Smith, Zhineng Fan, Kyu-hyoun Kim, Rocky Huang, Brian J. Connolly, Yifan Huang, Kyle Giesen, Luyun Yi
Publikováno v:
2019 IEEE 69th Electronic Components and Technology Conference (ECTC).
DDR5 Differential DIMM (DDIMM) is being defined in JEDEC and will be introduced to the market in 2020. DDR5 DDIMM uses OMI (OpenCAPI Memory Interface) as the host interface. On the DDIMM printed circuit board (PCB), the minimum data transfer rate per
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::e64e17093428f12f1ac91ce790568130
https://doi.org/10.1109/ectc.2019.00186
https://doi.org/10.1109/ectc.2019.00186
Autor:
Bulent Abali, Kyu-hyoun Kim, Seokin Hong, Michael B. Healy, Prashant J. Nair, Alper Buyuktosunoglu
Publikováno v:
MICRO
Memory systems are becoming bandwidth constrained and data compression is seen as a simple technique to increase their effective bandwidth. However, data compression requires accessing Metadata which incurs additional bandwidth overheads. Even after
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::733c6b2c203e25c1678134a6e0df07d0
https://doi.org/10.1109/micro.2018.00034
https://doi.org/10.1109/micro.2018.00034
Autor:
Dean Sanner, Charles Louis Haymes, Adam J. McPadden, Kyu-hyoun Kim, Sameh W. Asaad, Thomas Roewer, Daniel M. Dreps, Jan van Lunteren, Bharat Sukhwani
Publikováno v:
MICRO
We demonstrate the use of an FPGA as a memory buffer in a POWER8® system, creating a novel prototyping platform that enables innovation in the memory subsystem of POWER-based servers. Our platform, called ConTutto, is pin-compatible with POWER8 buff
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::8422b1c0c769791e551a8a145198cd50
https://doi.org/10.1145/3123939.3124535
https://doi.org/10.1145/3123939.3124535
Autor:
Kyu-hyoun Kim, In-Young Chung
Publikováno v:
IEICE Transactions on Electronics. :208-211
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::41f5e56dad4683021804da73869886fc
https://doi.org/10.1093/ietele/e90-c.1.208
https://doi.org/10.1093/ietele/e90-c.1.208
Autor:
Jung Sunwoo, Hoon Lee, Woo-Seop Kim, Moon-Sook Park, Kyu-hyoun Kim, Young-Chan Jang, Hoe-ju Chung, Chang-Hyun Kim, Su-Jin Chung, Duk-ha Park, Jae-Kwan Kim, Jin-Young Kim, Hyun-Kyung Kim, Hwan-Wook Park, Uk-Song Kang, Young-Taek Lee, Joo Sun Choi, Kee-Won Kwon, Hyung-seuk Kim
Publikováno v:
ISSCC
This paper proposes a deca-data rate clocking scheme and relevant I/O circuit techniques for a multi-Gb/s/pin memory interface. A deca-data rate scheme transmits 10 bits in one external clock cycle to transfer an error control code along with origina
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::459383a88b892d96879ad94fa0d7818a
https://doi.org/10.1109/jssc.2006.888297
https://doi.org/10.1109/jssc.2006.888297