Zobrazeno 1 - 10
of 14
pro vyhledávání: '"Kyu Nam Lim"'
Autor:
Gab-Soo Han, N.-W. Heo, Changsik Yoo, Duk-Min Lee, Gyung-Su Byun, Kye-Hyun Kyung, Lee Hyung-Kweon, Jun-Wan Chai, Hyoung-Chul Choi, Chun-Sup Kim, Hyun-su Choi, Sung-Yong Cho, Kyu-Nam Lim
Publikováno v:
IEEE Journal of Solid-State Circuits. 39:941-951
A 512-Mb DDR-II SDRAM has achieved 700-Mb/s/pin operation at 1.8-V supply voltage with 0.12-/spl mu/m DRAM process. The low supply voltage presents challenges in high data rate and signal integrity. Circuit techniques such as hierarchical I/O lines,
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::71acecf858b7a9d52d140fb1d66b7eea
https://doi.org/10.1109/jssc.2004.827806
https://doi.org/10.1109/jssc.2004.827806
Autor:
Hongil Yoon, Tae-Sung Jung, Chang-Ho Lee, Gi-Won Cha, Kyu-Nam Lim, Nam-jong Kim, Hongsik Jeong, Soo In Cho, Jun-Young Jeon, Kinam Kim, Keum-Yong Kim, Changsik Yoo, Tae-Young Chung, Kyu-Chan Lee
Publikováno v:
IEEE Journal of Solid-State Circuits. 34:1589-1599
A double data rate (DDR) at 333 Mb/s/pin is achieved for a 2.5-V, 1-Gb synchronous DRAM in a 0.14-/spl mu/m CMOS process. The large density of integration and severe device fluctuation present challenges in dealing with the on-chip skews, packaging,
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::d34fdcb9015f383af35f8e4eab34d1a1
https://doi.org/10.1109/4.799867
https://doi.org/10.1109/4.799867
Publikováno v:
Integrated Ferroelectrics. 17:97-104
A semi-empirical CAD model of ferroelectric capacitor for circuit simulation as well as for device characterization is proposed. The model can successfully describe the followings with only 5 parameters(Vc, Vo, Ps, Co, τ which have definite meanings
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::658302a433683e8397aec34b6cc0ef3c
https://doi.org/10.1080/10584589708012985
https://doi.org/10.1080/10584589708012985
Publikováno v:
Journal of Applied Physics. 74:3692-3697
The optimum barrier height of GaAs/AlxGa1−xAs multiple quantum well for the static property of the optical modulator is studied including exciton line broadening effects. The exciton binding energy, oscillator strength, and radius are calculated wi
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::7f0444b182c447d9e7be026fa3b31442
https://doi.org/10.1063/1.354515
https://doi.org/10.1063/1.354515
Autor:
Dong-Il Seo, Sang-Keun Kwak, Jei-Hwan Yoo, Ki-Chul Chun, Kyu-Nam Lim, Soo-In Cho, Jae-Yoon Sim, Young-Gu Gang, Joong-Yong Choi
Publikováno v:
2003 Symposium on VLSI Circuits. Digest of Technical Papers (IEEE Cat. No.03CH37408).
A 256 Mb SDRAM is implemented with a 0.12 /spl mu/m technology to verify two circuit schemes suitable for mobile application. A charge transferred presensing is proposed to achieve fast low-voltage sensing and robust operation. With a precharge disab
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::3c8d1036823430633e32d0f61abb70e7
https://doi.org/10.1109/vlsic.2003.1221230
https://doi.org/10.1109/vlsic.2003.1221230
Autor:
Kyu Nam Lim, Nam Jong Kim, Chang-Ho Lee, Jun Young Jeon, Tae Young Jeong, Soo In Cho, Gi Won Cha, Keum Yong Kim, Ki Nam Kim, Hongil Yoon, Tae-Sung Jung, Hongsik Jeong, Kyu Chan Lee, Changsik Yoo
Publikováno v:
1999 IEEE International Solid-State Circuits Conference. Digest of Technical Papers. ISSCC. First Edition (Cat. No.99CH36278).
While on-chip data flight times approach a few tens of nanoseconds for gigabit-scale DRAMs, a bandwidth over 250 MHz requires data input and output timing accuracy within 0.3 ns. Although a high-speed data interface can be achieved using precise cloc
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::64d34f7a4e5c767737d684d5b40c39cd
https://doi.org/10.1109/isscc.1999.759327
https://doi.org/10.1109/isscc.1999.759327
Autor:
Jae-hoon Joo, Soo-In Cho, Jin-Seok Lee, Sang-seok Kang, Younsang Lee, Jong-Hyun Choi, Byung-Il Ryu, Kyu-Nam Lim
Publikováno v:
2001 Symposium on VLSI Circuits. Digest of Technical Papers (IEEE Cat. No.01CH37185).
Two design techniques are presented to improve the yield of high density DRAM product. One is bit line coupling (BLC) scheme and the other is electrical fuse (E-Fuse) circuit for reliable field programmable repair scheme. We obtain an improvement of
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::65fc7ae540b5376d5a42edaf095009d2
https://doi.org/10.1109/vlsic.2001.934186
https://doi.org/10.1109/vlsic.2001.934186
Autor:
Keum Yong Kim, Nam Jong Kim, Hyun Lee, Dong Il Seo, Jae-Yoon Sim, Hongsik Jeong, Byung Il Ryu, Jaeyoung Lee, Chang Gyu Hwang, Kyu Nam Lim, Sang Man Byun, Chang Hyun Choi, Won Suk Yang, Jel Hwan Yoo, Kinam Kim, Hongil Yoon
Publikováno v:
2001 IEEE International Solid-State Circuits Conference. Digest of Technical Papers. ISSCC (Cat. No.01CH37177).
A 1.8 V 4 Gb DDR SDRAM for low voltage and high speed at full density has reduced inter-bitline coupling noise in the twisted open bit line architecture. Amplifier sensitivity and sensing margin are improved by gain-controlled pre-sensing and active
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::affd722f4694e8b6123a9b3310a3bd0d
https://doi.org/10.1109/isscc.2001.912681
https://doi.org/10.1109/isscc.2001.912681
Publikováno v:
Extended Abstracts of the 1996 International Conference on Solid State Devices and Materials.
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::3de90508e9bab6fc0486d81d2567c28c
https://doi.org/10.7567/ssdm.1996.pd-1-7
https://doi.org/10.7567/ssdm.1996.pd-1-7
Autor:
Jae-Yoon Sim, Young-Gu Gang, Kyu-Nam Lim, Joong-Yong Choi, Sang-Keun Kwak, Ki-Chul Chun, Jei-Hwan Yoo, Dong-Il Seo, Soo-In Cho
Publikováno v:
2003 Symposium on VLSI Circuits. Digest of Technical Papers (IEEE Cat. No.03CH37408); 2003, p289-292, 4p