Zobrazeno 1 - 9
of 9
pro vyhledávání: '"Kyoji Mizoguchi"'
Autor:
Kazutoshi Kodama, Yusuke Sato, Yuhi Yorikado, Raphael Berner, Kyoji Mizoguchi, Takahiro Miyazaki, Masahiro Tsukamoto, Yoshihisa Matoba, Hirotaka Shinozaki, Atsumi Niwa, Tetsuji Yamaguchi, Christian Brandli, Hayato Wakabayashi, Yusuke Oike
Publikováno v:
2023 IEEE International Solid- State Circuits Conference (ISSCC).
Autor:
Atsumi Niwa, Futa Mochizuki, Raphael Berner, Takuya Maruyarma, Toshio Terano, Kenichi Takamiya, Yasutaka Kimura, Kyoji Mizoguchi, Takahiro Miyazaki, Shun Kaizu, Hirotsugu Takahashi, Atsushi Suzuki, Christian Brandli, Hayato Wakabayashi, Yusuke Oike
Publikováno v:
2023 IEEE International Solid- State Circuits Conference (ISSCC).
Autor:
Hikaru Watanabe, Shun Suzuki, Toshiki Nakamura, Keita Mizushina, Ken Takeuchi, Kyoji Mizoguchi, Yoshiaki Deguchi
Publikováno v:
A-SSCC
This paper proposes Privacy-aware Data-Lifetime Control NAND Flash System (PDLCS), which changes the data-lifetime flexibly for the right to be forgotten. This system realizes both short and long term data-lifetime by In-3D Vertical Cell Processing.
Publikováno v:
2019 Silicon Nanoelectronics Workshop (SNW).
This paper proposes Less Reliable Page Error Reduction (LRPER) to achieve both high reliability and small data overhead of 3D-TLC NAND flash memories. LRPER suppresses both lateral charge migration and vertical charge de-trap without redundant readin
Publikováno v:
IRPS
This paper proposes Automatic Data Repair Overwrite Pulse (ADROP) to improve the reliability of 3D-TLC NAND flash. When ECC cannot correct errors, ADROP overwrites data including errors to failed memory cells and thus adaptively injects electrons to
Publikováno v:
IRPS
Cross Error Elimination (XEE) ECC with Horizontal Error Detection (HED) and Vertical-LDPC (V-LDPC) is proposed to extend the data-retention lifetime of 3D-TLC NAND flash-based SSD. HED improves the error correction capability of LDPC ECC by evaluatin
Publikováno v:
2017 IEEE International Electron Devices Meeting (IEDM).
Vth Nearing is proposed to suppress the lateral charge migration and to improve the reliability of 3D TLC NAND flash. By modulating the write data so that V th of adjacent cells become close, the data-retention errors decrease by 40%. The acceptable
Publikováno v:
2017 IEEE International Memory Workshop (IMW).
Data-retention characteristics of 3-dimensional (3D) NAND flash memory have been evaluated with the optimal Vref (read reference voltage) shift in comparison with 2-dimentional (2D) (1Xnm) NAND flash memory. Bit-error rate (BER) of data-retention and
Publikováno v:
2017 IEEE International Reliability Physics Symposium (IRPS).
RTN (Random Telegraph Noise) impact on data-retention failure/recovery mechanism has been investigated in scaled (∼1Ynm) 2-dimensional (2D) TLC (3bits/cell) NAND flash memories. The data-retention failure is caused by the electron de-trapping from