Zobrazeno 1 - 10
of 16
pro vyhledávání: '"Kwang-jin Moon"'
Autor:
Lee Hakseung, Yi-koan Hong, Hyokyung Cho, SeonKwan Hwang, Tae-Seong Kim, Hoon-joo Na, Kyu-Ha Lee, Ki-Hyun Hwang, Sohye Cho, Kwang-jin Moon
Publikováno v:
2021 IEEE 71st Electronic Components and Technology Conference (ECTC).
3D Multi-stacking technology using Cu-Cu hybrid wafer bonding has been developed to achieve superior power, speed performances and higher density with minimized form factor. To realize multi-stacked device by using Wafer on wafer (WoW) bonding, both
Autor:
Tae-Young Kim, Kwang-jin Moon, Seok-Ho Kim, Seong-min Son, Geun Young Yeom, Ki-Hyun Hwang, Kim Hoechul, Jin-Nam Kim, Hyung-Jun Jeon, Junhong Min, Hoon-joo Na, Eunsuk Jung
Publikováno v:
2020 IEEE 70th Electronic Components and Technology Conference (ECTC).
The low-temperature wafer bonding has been studied on two types of dielectric material (SiO, SiCN) as final bonding layers. It is important for the wafer bonding technology to obtain the higher interfacial energy between two bonding wafers, and oxyge
Autor:
Hoon-joo Na, Seok-Ho Kim, Kwang-jin Moon, Kim Taeyeong, Ki-Hyun Hwang, Pil-Kyu Kang, Kyu-Ha Lee, Joo-Hee Jang, Sang-Jin Hyun
Publikováno v:
2019 IEEE 69th Electronic Components and Technology Conference (ECTC).
The scaling of semiconductor device below 10nm has faced the higher process difficulty and longer development periods. Three-dimensional integrated circuits (3D IC) using chip partitioning and wafer-to-wafer bonding have been acknowledged as the next
Autor:
Kwang-jin Moon
Publikováno v:
Journal of CheongRam Korean Language Education. :251-283
Autor:
Yeong-lyeol Park, Ki-Young Yun, Jiwoong Sue, Kwang-jin Moon, Chilhee Chung, So-Young Lee, Jin-ho An, Gil-heyun Choi, Byung-lyul Park, Ho-Jun Lee, Ho-Kyu Kang, Do-Sun Lee
Publikováno v:
2012 IEEE International Interconnect Technology Conference.
Stresses induced by the large volume of Cu in Through Silicon Vias (TSV) can result in global/local Cu extrusion which may affect reliability in 3D chip stacking technologies beyond the 28 nm node for high performance mobile devices. In this work, TS
Autor:
null DeokYoung Jung, null Kwang-Jin Moon, null Byung-Lyul Park, null Gilheyun Choi, null Ho-Kyu Kang, null Chilhee Chung, null Deok Young Jung, null Yonghan Rho
Publikováno v:
2012 SEMI Advanced Semiconductor Manufacturing Conference.
As semiconductor performance improvements through device scale-down becomes more difficult, 3D chip stacking technology with TSVs (Through Silicon Via) is becoming an increasingly attractive solution to achieve higher system performances by way of hi
Autor:
June Moon, Kwang-jin Moon, Sang-Bom Kang, Hyung-Gon Kim, Woong-Hee Sohn, N.J. Bae, Suk-pil Kim, G.H. Choi, U. I. Chung
Publikováno v:
IEEE International Electron Devices Meeting 2003.
A novel CVD-cobalt process which enables a uniform salicidation even in novel MOS device structures with complex shape is developed for the first time. With CVD-cobalt salicidation, identical values of low sheet resistance can be realized on actives
Autor:
Joo-Tae Moon, Jong-Ho Yun, Hyun-Su Kim, Gil-heyun Choi, U-In Chung, Sung-tae Kim, Woong-Hee Sohn, Sug-Woo Jung, Kwang-jin Moon, Seong-hwee Cheong, Se-Hoon Kim, Nam-Jin Bae
Publikováno v:
Extended Abstracts of the 2004 International Conference on Solid State Devices and Materials.
Publikováno v:
Proceedings of the IEEE 1998 International Interconnect Technology Conference (Cat. No.98EX102).
The electrical characteristics of PECVD-WN/sub x/ and CVD-TiN films as the upper electrode for Ta/sub 2/O/sub 5/ capacitors were compared in a 3D stack structure. In terms of step coverage, CVD-TiN shows excellent results of about 90% at the stack st
Autor:
Gil Heyun Choi, Myoung Bum Lee, Sang Bom Kang, Kwang Jin Moon, Young Wook Park, Hee Sook Park, Joo Tae Moon
Publikováno v:
2001 International Symposium on VLSI Technology, Systems, and Applications. Proceedings of Technical Papers (Cat. No.01TH8517).
The implementation of W bit-line enabled the integration of n+ and p+ common contact process at bit-line level. Despite the advantages of the common contact process such as chip-area reduction and elimination of the burden associated with MC dry etch