Zobrazeno 1 - 6
of 6
pro vyhledávání: '"Kwang-Ok Koh"'
Autor:
Sang-Hun Seo, Kyeong-Tae Kim, Kwang-Ok Koh, Moo-sung Kim, Won-suk Yang, Han-sin Lee, Seung-Hyun Park
Publikováno v:
IEEE Electron Device Letters. 23:719-721
A new double offset-implanted (DOI) technology, which can effectively suppress the gate-induced drain-leakage (GIDL) current of buried-channel PMOS transistor in small-size CMOS devices, is proposed and developed with a 0.12-/spl mu/m single-gate low
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::b4c2acd9dc9205e4453b7a55a06fb313
https://doi.org/10.1109/led.2002.805769
https://doi.org/10.1109/led.2002.805769
Autor:
Jin-Ho Kim, Jongchol Shin, Kang-Bok Lee, Kwang-Ok Koh, Seok-Ha Lee, Jongwan Jung, Duck-Hyung Lee, Doo-Won Kwon, Kinam Kim, Chang-Rok Moon, Hyun-Pil Noh, D. Park, H.S. Jeong
Publikováno v:
2006 International Electron Devices Meeting.
Technology and characteristics of 8-mega density CMOS image sensor (CIS) with unit pixel size of 1.75times1.75mum2 are introduced. With recessed transfer gate (RTG) structure and other sophisticated process/device technology, remarkably enhanced satu
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::7daa2418a85f65d4932a93f9469ba773
https://doi.org/10.1109/iedm.2006.346975
https://doi.org/10.1109/iedm.2006.346975
Autor:
K.C. Kim, Kwang Pyuk Suh, Nae-In Lee, S.T. Kang, Sun-Ghil Lee, Jung-hyeon Kim, Suk-pil Kim, I.S. Park, M.C. Kim, Seo Minwoong, H.-K. Kang, Geum-Jong Bae, I.W. Cho, Sei-jin Kim, Kwang-Ok Koh
Publikováno v:
2003 Symposium on VLSI Technology. Digest of Technical Papers (IEEE Cat. No.03CH37407).
A new Local SONOS structure has been proposed for an embedded NVM cell in 0.13 /spl mu/m standard CMOS logic process. The localized storage silicon nitride layer of Local SONOS cell provides the essential properties for the embedded NVM such as the c
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::306aed91b1f4411ae059631ad62bfcfe
https://doi.org/10.1109/vlsit.2003.1221071
https://doi.org/10.1109/vlsit.2003.1221071
Autor:
Jung-hyeon Kim, S.D. Chae, C.W. Kim, S.A. Seo, Suk-pil Kim, Nae-In Lee, Hwang So-Hee, I.W. Cho, Geum-Jong Bae, Seung-Kwon Kim, B.R. Lim, M.C. Kim, B.J. Lee, H.-K. Kang, D.Y. Lee, K.C. Kim, Seo Minwoong, Sei-jin Kim, Kwang-Ok Koh
Publikováno v:
Digest of Technical Papers. 2004 Symposium on VLSI Technology, 2004..
We have successfully integrated 8M bits Localized ONO Memory (LONOM) for the embedded nonvolatile memory using 0.13um standard logic process with 5-level Cu metallization. which has a small cell size of 0.276UM and the simplest cell array structure.
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::28c5dbefc441e2019896deee3319fc8a
https://doi.org/10.1109/vlsit.2004.1345502
https://doi.org/10.1109/vlsit.2004.1345502
Autor:
Jae-Hun Jeong, Jae-Kyun Park, Moon Yong Lee, C.Y. Chang, Kwang-Ok Koh, Hyung-Shin Kwon, Wonseok Cho, Kinam Kim, Donggun Park, Gyu-Ho Lyu, Young-Chul Jang, Hoon Lim, Sung-Bong Kim, Hee-Soo Kang, Soon-Moon Jung, Joonbum Park, Young-Seop Rah
Publikováno v:
Digest. International Electron Devices Meeting.
The smallest SRAM cell, 0.79 /spl mu/m/sup 2/, was realized by a revolutionary cell layout, fine tuned OPC technique to overcome the 248 nm KrF lithography limitation, instead of using 193 nm ArF lithography. Sub-100 nm CMOS technology was indispensa
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::c91eb51fe50f57f62df3426019604070
https://doi.org/10.1109/iedm.2002.1175868
https://doi.org/10.1109/iedm.2002.1175868
Autor:
Jung-In Hong, Yong Park, Sung-Bong Kim, Joon-Yong Joo, Moosung Kim, Han-Shin Lee, Jin-Ho Kim, Suk-Joo Lee, Seung-Hyun Park, Byung-Joon Hwang, Jai-Kyun Park, Kwang-Ok Koh, Moonyong Lee, Ji-Young Lee, Do-hyung Kim
Publikováno v:
International Electron Devices Meeting. Technical Digest (Cat. No.01CH37224).
We have developed a 1.29 um2 full CMOS SRAM cell for low power applications, which is the world-smallest one by using 0.12 um single gate CMOS technology and optical enhancement techniques for extending use of 248 nm KrF lithography. It includes (1)
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::dba923c70ee9ceb3263524f24d8d8e4c
https://doi.org/10.1109/iedm.2001.979478
https://doi.org/10.1109/iedm.2001.979478