Zobrazeno 1 - 10
of 14
pro vyhledávání: '"Kwang-Myoung Rho"'
Autor:
Ki-Seon Park, Tsuneo Inaba, Hiromi Noro, Jonghoon Oh, Sung-Woong Chung, Akihito Yamamoto, Hyeongon Kim, Hisato Oyamatsu, Kazumasa Sunouchi, Jinwon Park, Yutaka Shirai, Seoung-Ju Chung, Dong-Keun Kim, Kenji Tsuchida, Ji-Hyae Bae, Hyunin Moon, Kwang-Myoung Rho
Publikováno v:
ISSCC
Spin-transfer torque magnetic RAM (STT-MRAM) is one of the most promising nonvolatile memories with guaranteed high-speed read and write operations. Along with performance improvements in the tunnel magnetoresistance (TMR) and the magnetic tunnel jun
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::4f5e7dd5fe478f795d6d980cb7a53276
https://doi.org/10.1109/isscc.2017.7870428
https://doi.org/10.1109/isscc.2017.7870428
Autor:
Kazumasa Sunouchi, Kyoung-Hwan Park, Guk-Cheon Kim, Kwang-Myoung Rho, Haruichi Kanaya, Suock Chung, Akihito Yamamoto, K. Noma, J. Y. Yi, Kenji Tsuchida, Tatsuya Kishi, Toshihiko Nagase, Mun-Haeng Lee, Yun-Seok Chun, S. J. Hong, Sung-Woong Chung, Hisato Oyamatsu, Hyeongon Kim, Jeongsoo Park, Masahisa Yoshikawa
Publikováno v:
2016 IEEE International Electron Devices Meeting (IEDM).
For the first time, 4Gbit density STT-MRAM using perpendicular MTJ in compact cell was successfully demonstrated through the tight distributions for resistance and magnetic properties. This paper includes the results regarding parasitic resistance co
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::e28a3cfd830ac5b0b140063b0a64ec20
https://doi.org/10.1109/iedm.2016.7838490
https://doi.org/10.1109/iedm.2016.7838490
Publikováno v:
IEEE Journal of Solid-State Circuits. 31:1025-1028
A new offset-trimming bit-line sensing scheme is described which is suitable for gigabit-scale DRAM's. This sensing scheme can suppress the sensitivity degradation caused by the large electrical parameter variation of deep submicron transistors. The
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::ce7e2101dc15b60ca3f62f33795803a9
https://doi.org/10.1109/4.508216
https://doi.org/10.1109/4.508216
Publikováno v:
ICVC '99. 6th International Conference on VLSI and CAD (Cat. No.99EX361).
In this paper, we propose novel interface circuits using Dynamic Over-Driving (DOD) and Adaptive Sensing (AS) scheme for high speed and energy-efficient interface on a chip. Our AS-receiver makes it possible to use very low swing because of its good
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::afe91d431b3fd78eca51a982f1dcdde0
https://doi.org/10.1109/icvc.1999.820940
https://doi.org/10.1109/icvc.1999.820940
Autor:
Myoung Jun Chung, Yo Hwan Koh, Kwang Myoung Rho, Chan Kwang Park, Ha Poong Chung, Dai Hoon Lee, Seong Min Hwang
Publikováno v:
1995 IEEE TENCON. IEEE Region 10 International Conference on Microelectronics and VLSI. 'Asia-Pacific Microelectronics 2000'. Proceedings.
With the MOSES (Mask Oxide Sidewall Etch Scheme) process which uses a conventional i-line stepper and isotropic wet etching, CMOSFETs with fine gate patterns of 0.1 /spl mu/m or less are fabricated and characterized successfully. To improve the short
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::3630e9adc127e188d06a144c523ecd2e
https://doi.org/10.1109/tencon.1995.496397
https://doi.org/10.1109/tencon.1995.496397
Autor:
Kwang Myoung Rho, Yo Hwan Koh, Seong Min Hwang, Dai-Hoon Lee, Chan Kwang Park, Myoung Jun Chung
Publikováno v:
1995 International Symposium on VLSI Technology, Systems, and Applications. Proceedings of Technical Papers.
A novel structure for high performance deep submicron MOSFETs, which is called the SAW (Self-Aligned selectively grown W-gate) MOSFET, is proposed. The SAW MOSFET structure has extremely low gate resistance due to the use of tungsten as gate electrod
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::5fbe645ebb20254f71a6bcafe54bd57b
https://doi.org/10.1109/vtsa.1995.524701
https://doi.org/10.1109/vtsa.1995.524701
Publikováno v:
MTDT
An orthogonal RAM cell array architecture suitable for efficient transposing is proposed, and layout and simulation results are presented. The cell is developed to adopt folded bit-line sensing scheme area-efficiently. The proposed alternate bit-line
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::43f09e2e03262b4349c8d0a84f82e8dc
https://doi.org/10.1109/mtdt.2001.945222
https://doi.org/10.1109/mtdt.2001.945222
A high performance deep submicron MOSFET structure with self-aligned selectively grown W-gate (SAW).
Autor:
Yo Hwan Koh, Chan Kwang Park, Seong Min Hwang, Kwang Myoung Rho, Myoung Jun Chung, Dai-Hoon Lee
Publikováno v:
1995 International Symposium on VLSI Technology, Systems & Applications Proceedings of Technical Papers; 1995, p268-272, 5p
Autor:
Kwang Myoung Rho, Yo Hwan Koh, Chan Kwang Park, Seong Min Hwang, Ha Poong Chung, Myoung Jun Chung, Dai Hoon Lee
Publikováno v:
1995 IEEE TENCON IEEE Region 10 International Conference on Microelectronics & VLSI 'Asia-Pacific Microelectronics 2000' Proceedings; 1995, p291-294, 4p
Publikováno v:
ICVC '99 6th International Conference on VLSI & CAD (Cat No99EX361); 1999, p388-391, 4p