Zobrazeno 1 - 10
of 14
pro vyhledávání: '"Kwang-Chun Choi"'
Publikováno v:
IEEE Transactions on Circuits and Systems II: Express Briefs. 61:319-323
A 0.4-V phase-locked loop (PLL) that has much improved power efficiency is realized in standard 65-nm CMOS. The PLL employs a novel ultralow-voltage charge pump that compensates current mismatch with an active loop filter and produces significantly r
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::bbdd6bc20e8f45e7d6306ce7c056eb20
https://doi.org/10.1109/tcsii.2014.2312800
https://doi.org/10.1109/tcsii.2014.2312800
Publikováno v:
IEEE Transactions on Circuits and Systems II: Express Briefs. 60:311-315
A low-power 1.6-GHz phase-locked loop (PLL) based on a novel supply-regulated voltage-controlled oscillator (SR-VCO) including an active-loop filter (ALF) is realized. In this PLL, an active RC filter is combined with SR-VCO, achieving the advantages
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::1a39e034066a275fd111942695d9f64f
https://doi.org/10.1109/tcsii.2013.2258253
https://doi.org/10.1109/tcsii.2013.2258253
Publikováno v:
Journal of the Institute of Electronics Engineers of Korea. 50:122-133
An arbiter-based simple phase decision circuit (PDC) optimized for high-resolution phase-to-digital converter made up of an analog phase-frequency detector and a time-to-digital converter for all-digital phase-locked loops is proposed. It can disting
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::382fdb4353bf58a3bf69380a2a38df20
https://doi.org/10.5573/ieek.2013.50.2.122
https://doi.org/10.5573/ieek.2013.50.2.122
Publikováno v:
IEEE Transactions on Circuits and Systems II: Express Briefs. 59:143-147
A new type of sampling error corrector for a time- to-digital converter (TDC) having a multiphase reference clock and a binary counter is demonstrated. With this corrector, sampling errors caused by asynchronous TDC inputs are corrected without requi
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::f3786f40ab78aa300c3dc0cd344ea803
https://doi.org/10.1109/tcsii.2012.2184370
https://doi.org/10.1109/tcsii.2012.2184370
Publikováno v:
IEICE Transactions on Electronics. :1704-1707
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::ce8488c077a5daa2df99173180d7b619
https://doi.org/10.1587/transele.e93.c.1704
https://doi.org/10.1587/transele.e93.c.1704
Publikováno v:
IEEE Journal of Solid-State Circuits. 43:2284-2292
A new mixed-mode binary phase shift keying (BPSK) demodulator is demonstrated using a half-rate bang-bang phase detector commonly used in clock and data recovery (CDR) applications. This demodulator can be used for new home networking applications us
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::d8bf91cdc67fdc567177ea97db8e75f0
https://doi.org/10.1109/jssc.2008.2004327
https://doi.org/10.1109/jssc.2008.2004327
Publikováno v:
IEEE Photonics Technology Letters. 24:1112-1114
We demonstrated a silicon photonics-wireless interface integrated circuit (IC) realized in 0.25- μ m SiGe bipolar complementary metal-oxide-semiconductor technology, which converts 850-nm optical nonreturn-to-zero data into 60-GHz binary phase-shift
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::35414360714d1e33af9109c214998997
https://doi.org/10.1109/lpt.2012.2196034
https://doi.org/10.1109/lpt.2012.2196034
Publikováno v:
2013 International SoC Design Conference (ISOCC).
An ultra-low voltage phase-locked loop (PLL) is demonstrated in standard 130-nm CMOS technology. The PLL employs a novel low-voltage charge-pump circuit which compensates current and leakage mismatches that result in suppressed reference spurs. Its v
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::12b03c82b4fad97cd0850fa2ecd86af3
https://doi.org/10.1109/isocc.2013.6864005
https://doi.org/10.1109/isocc.2013.6864005
Publikováno v:
ISOCC
This paper reports a 10-Gb/s power and area efficient clock and data recovery circuit implemented in 65-nm CMOS technology. CMOS static circuits are used as much as possible so that the power consumption and the chip area can be minimized. In order t
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::c28ba75f185081b1654ffda3944c490c
https://doi.org/10.1109/isocc.2012.6407050
https://doi.org/10.1109/isocc.2012.6407050
Publikováno v:
2008 IEEE Asian Solid-State Circuits Conference.
A mixed-mode high-speed binary phase-shift keying (BPSK) demodulator for IEEE802.15.3c mm-wave wireless personal area network (WPAN) application is realized with 0.18 mum CMOS process. The demodulator core consumes 23.4 mW from 1.8 V power supply whi
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::8dc800e04d656f6ce9be2ae006ff2801
https://doi.org/10.1109/asscc.2008.4708801
https://doi.org/10.1109/asscc.2008.4708801