Zobrazeno 1 - 6
of 6
pro vyhledávání: '"Kushagra Bhatheja"'
Autor:
Kushagra Bhatheja, Shravan Chaganti, Degang Chen, Xiankun Robert Jin, Chris C Dao, Juxiang Ren, Abhishek Kumar, Daniel Correa, Mark Lehmann, Thomas Rodriguez, Eric Kingham, Joel R Knight, Allan Dobbin, Scott W Herrin, Doug Garrity
Publikováno v:
2022 IEEE International Test Conference (ITC).
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::60b842bc343bd0192b794ef13f51ac56
https://doi.org/10.1109/itc50671.2022.00063
https://doi.org/10.1109/itc50671.2022.00063
Publikováno v:
IEEE Transactions on Circuits and Systems II: Express Briefs. 68:1690-1694
Extensive use of electronic components in mission critical applications has brought reliability concerns in VLSI to the forefront. Ageing related reliability effects such as Time Dependent Dielectric Breakdown (TDDB) might lead to in-field chip failu
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::e82439c7b0ee93ed1dd86e75f2305ec1
https://doi.org/10.1109/tcsii.2021.3068628
https://doi.org/10.1109/tcsii.2021.3068628
Publikováno v:
2022 IEEE International Symposium on Circuits and Systems (ISCAS).
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::2c4b69c5d59f157307bec00282937f14
https://doi.org/10.1109/iscas48785.2022.9937694
https://doi.org/10.1109/iscas48785.2022.9937694
Publikováno v:
MWSCAS
NBTI is one of the primary concerns for long-term reliability in systems using deep submicron technologies. In this paper, we propose a simple on-chip sensor architecture that monitors degradation due to NBTI through pseudo-static measurements of the
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::d6168773914629d5ea56873d6db27343
https://doi.org/10.1109/mwscas47672.2021.9531715
https://doi.org/10.1109/mwscas47672.2021.9531715
Publikováno v:
MWSCAS
Increasing demand for higher data transfer rates is bringing 4 level pulse amplitude modulation (PAM4) scheme to the forefront of high-speed serial link design. Jitter estimation is an important part of high-speed serial link design and testing. This
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::9b09d7dcfedb4df958f486d6bcfbde92
https://doi.org/10.1109/mwscas48704.2020.9184474
https://doi.org/10.1109/mwscas48704.2020.9184474
Publikováno v:
2013 IEEE 22nd Conference on Electrical Performance of Electronic Packaging and Systems.
Random jitter (RJ) estimation based on Tail Fit algorithm are generally inaccurate in presence of deterministic components like the presence of sinusoidal jitter (SJ) and duty cycle distortion (DCD). Addition of deterministic jitter changes the stand
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::c23514cbe0ea0c8486ce21b2527334a4
https://doi.org/10.1109/epeps.2013.6703487
https://doi.org/10.1109/epeps.2013.6703487