Zobrazeno 1 - 10
of 96
pro vyhledávání: '"Kurt Antreich"'
Autor:
Andrew B. Kahng
Publikováno v:
Proceedings of the 2015 Symposium on International Symposium on Physical Design.
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::4f575535a0f14993ba52e8fa8b7bab79
https://doi.org/10.1145/3253994
https://doi.org/10.1145/3253994
Publikováno v:
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems. 26:1733-1748
This paper presents two simulation-based methods for the calculation of the feasible performance values of analog integrated circuits. The first method computes the Pareto-optimal tradeoffs of competing performances at full simulator accuracy. Additi
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::9f945193b847db9d14590333d33a3204
https://doi.org/10.1109/tcad.2007.895756
https://doi.org/10.1109/tcad.2007.895756
Publikováno v:
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems. 19:907-927
Implication, justification, and propagation are three important Boolean problems that have to be solved during many tasks in electronic design automation (EDA) for digital circuits. As they constitute the key components of automatic test pattern gene
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::89d90c5c816c6672fc95afc96b54f9f8
https://doi.org/10.1109/43.856977
https://doi.org/10.1109/43.856977
Publikováno v:
ACM Transactions on Design Automation of Electronic Systems. 4:313-350
Functional decomposition is an important technique for technology mapping to look up table-based FPGA architectures. We present the theory of and a novel approach to functional disjoint decomposition of multiple-output functions, in which common subf
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::a89820cbd1227a4456ae737f2b00a03f
https://doi.org/10.1145/315773.315783
https://doi.org/10.1145/315773.315783
Publikováno v:
itit. 41:42-45
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::79feb6fbd217028a80f5348cc5281054
https://doi.org/10.1524/itit.1999.41.2.42
https://doi.org/10.1524/itit.1999.41.2.42
Publikováno v:
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems. 18:1353-1368
This paper presents a new approach to the test design of analog circuits, called characteristic observation inference (COI). The COI method considers parametric as well as catastrophic faults. A strict distinction between the operational environment,
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::3c41abb27f9df94a6241ad24d1614568
https://doi.org/10.1109/43.784126
https://doi.org/10.1109/43.784126
Publikováno v:
Journal of Electronic Testing. 11:227-245
Automatic test pattern generation (ATPG) remains one of the most complex CAD tasks. Therefore, numerous methods were proposed to speed up ATPG by using parallelism. In this paper, we focus on parallelizing ATPG for stuck-at faults in sequential circu
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::de762e78ea2bad631816a7a9d01b34d6
https://doi.org/10.1023/a:1008266422380
https://doi.org/10.1023/a:1008266422380
Publikováno v:
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems. 13:57-71
In this paper, a new methodology for integrated circuit design considering the inevitable manufacturing and operating tolerances is presented. It is based on a new concept for specification analysis that provides exact worst-case transistor model par
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::4a32fedc3de556e68454c663ce58038d
https://doi.org/10.1109/43.273749
https://doi.org/10.1109/43.273749
Publikováno v:
International Journal of High Speed Electronics and Systems. :261-282
Worst-case analysis is commonly used in integrated circuit design to verify a satisfactory circuit performance with regard to changes in the manufacturing conditions. However, worst-case analysis is often carried out using approximate worst-case para
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::37429ad8585bd31648f7a1faeedae23f
https://doi.org/10.1142/s0129156493000121
https://doi.org/10.1142/s0129156493000121
Publikováno v:
ICCAD
Analog performance space exploration identifies the range of feasible performance values of a given circuit topology. It is an extremely challenging task of great importance to topology selection and hierarchical sizing. In this paper, a novel techni
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::4304bb8991b0a045cbf2ced850b4d185
https://doi.org/10.1109/iccad.2004.1382693
https://doi.org/10.1109/iccad.2004.1382693