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pro vyhledávání: '"Kunlei Gu"'
Publikováno v:
2021 China Semiconductor Technology International Conference (CSTIC).
In this paper, the impact of gate length on Single Event Upset (SEU) characteristics of 14 nm bulk and SOI FinFET 6T SRAM is investigated and compared by mixed-mode 3D TCAD simulation. Simulation results show that for both bulk and SOI FinFET SRAM ce