Zobrazeno 1 - 10
of 40
pro vyhledávání: '"Kunhyuk Kang"'
Publikováno v:
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems. 29:497-502
In multiple input switching (MIS) analysis, input signal alignment is one of the key factors which determines the quality and the accuracy of the approach. In this paper, we propose a new signal alignment methodology for MIS analysis based on a trans
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::39cf37932408e34f3576388c9c427a34
https://doi.org/10.1109/tcad.2009.2035482
https://doi.org/10.1109/tcad.2009.2035482
Publikováno v:
IEEE Transactions on Very Large Scale Integration (VLSI) Systems. 18:270-280
Performance variability in digital integrated circuits can largely affect parametric yield and product reliability in ultra deep submicrometer technologies. As a result, variation resilience is becoming an essential design requirement for future tech
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::5b4bbdbc72fc7466372dec5d674d0abf
https://doi.org/10.1109/tvlsi.2008.2010399
https://doi.org/10.1109/tvlsi.2008.2010399
Publikováno v:
IEEE Design & Test of Computers. 26:8-17
Bias temperature instability (BTI) is one of the major reliability challenges in nanoscale CMOS technology. This article investigates the severity of such degradation in logic and memory circuits. The simulation results reveal that BTI poses severe c
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::b7a54598f587fb91f49c1d5aef3842c9
https://doi.org/10.1109/mdt.2009.154
https://doi.org/10.1109/mdt.2009.154
Publikováno v:
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems. 28:46-59
Low-temperature polycrystalline-silicon thin-film transistor (LTPS TFT) has emerged as one of the promising candidates for low-power low-cost applications on flexible substrates. In this paper, we propose a statistical simulation methodology to estim
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::158f1dcd407be888bce329d49f963f4c
https://doi.org/10.1109/tcad.2008.2009149
https://doi.org/10.1109/tcad.2008.2009149
Publikováno v:
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems. 26:1770-1781
One of the major reliability concerns in nanoscale very large-scale integration design is the time-dependent negative- bias-temperature-instability (NBTI) degradation. Due to the higher operating temperature and increasing vertical oxide field, thres
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::501c40d6470a378cc9b74f523642bb66
https://doi.org/10.1109/tcad.2007.896317
https://doi.org/10.1109/tcad.2007.896317
Publikováno v:
IEEE Transactions on Very Large Scale Integration (VLSI) Systems. 15:660-671
Dual-Vt design technique has proven to be extremely effective in reducing subthreshold leakage in both active and standby mode of operation of a circuit in submicrometer technologies. However, aggressive scaling of technology results in different lea
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::70c80a346457287cf9e8057f3118cf9d
https://doi.org/10.1109/tvlsi.2007.898683
https://doi.org/10.1109/tvlsi.2007.898683
Publikováno v:
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems. 26:743-751
Negative bias temperature instability (NBTI) has become one of the major causes for temporal reliability degradation of nanoscale circuits. In this paper, we analyze the temporal delay degradation of logic circuits due to NBTI. We show that knowing t
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::0c1e3b4011b845b8da44801fd304e007
https://doi.org/10.1109/tcad.2006.884870
https://doi.org/10.1109/tcad.2006.884870
Publikováno v:
ACM Transactions on Design Automation of Electronic Systems. 11:848-879
Variability in process parameters is making accurate timing analysis of nano-scale integrated circuits an extremely challenging task. In this article, we propose a new algorithm for statistical static timing analysis (SSTA) using levelized covariance
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::5bcc5384cad84b460863e3cc4c563fe6
https://doi.org/10.1145/1179461.1179464
https://doi.org/10.1145/1179461.1179464
Publikováno v:
2008 Asia and South Pacific Design Automation Conference.
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::4bfa97eac2d30988574b19a1f35b7e37
https://doi.org/10.1109/aspdac.2008.4484047
https://doi.org/10.1109/aspdac.2008.4484047
Publikováno v:
2007 14th International Symposium on the Physical and Failure Analysis of Integrated Circuits.
We review the literature for reliability- and process-variation aware VLSI design to find that an exciting area of research/application is rapidly emerging as a core topic of IC design. Design of reliable circuits with unreliable component is a signi
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::02ecc8050907017b0f634ded4aafa2dc
https://doi.org/10.1109/ipfa.2007.4378050
https://doi.org/10.1109/ipfa.2007.4378050