Zobrazeno 1 - 10
of 53
pro vyhledávání: '"Kundan Nepal"'
Publikováno v:
International Journal of Parallel, Emergent and Distributed Systems. 37:696-713
Publikováno v:
Journal of Electronic Testing.
Test sets that target standard fault models may not always be sufficient for detecting all defects. To evaluate test sets for the detection of unmodeled defects, n-detect test sets (which detect all modeled faults at least n times) have previously be
Autor:
Kundan Nepal, Jennifer Dworak, Alfred L. Crouch, Soha Alhelaly, Ping Gui, Theodore W. Manikas
Publikováno v:
IEEE Transactions on Emerging Topics in Computing. 9:774-786
3D integrated circuits introduce both advantages and disadvantages for security. Among the disadvantages unique to 3D is the potential insertion of a Trojan die into the stack between two legitimate dies. Such a die could be used to snoop information
Publikováno v:
2022 IEEE 31st Microelectronics Design & Test Symposium (MDTS).
Autor:
Kundan Nepal, Jennifer Dworak, Fanchen Zhang, Theodore W. Manikas, Hui Jiang, Yi Sun, R. Iris Bahar
Publikováno v:
Journal of Electronic Testing. 35:887-900
We propose an architecture for a Field Programmable Gate Array (FPGA) based tester for a 3D stacked integrated circuit (IC). Due to the very short distances between dies in a stack that can make SerDes connections very efficient and the high density
Publikováno v:
2013 ASEE Annual Conference & Exposition Proceedings.
Autor:
Maurice Aburdene, Kundan Nepal
Publikováno v:
2011 ASEE Annual Conference & Exposition Proceedings.
Autor:
Kundan Nepal, Andrew Tubesing
Publikováno v:
2014 ASEE Annual Conference & Exposition Proceedings.
Publikováno v:
CCWC
A cost effective, easily scalable, and application independent FPGA cluster co-processing platform for machine learning (ML) applications is proposed. The work in this paper focuses on delivering an economical platform for the researchers and develop