Výsledky vyhledávání - "Kunal Godbole"

A 28-nm 75-fsrms Analog Fractional-$N$ Sampling PLL With a Highly Linear DTC Incorporating Background DTC Gain Calibration and Reference Clock Duty Cycle Correction

Autor: Yongping Han, Yongrong Zuo, Chih-Wei Yao, Ashutosh Verma, Pei-Yuan Chiang, Wanghua Wu, Ivan Siu-Chuang Lu, Sang Won Son, Thomas Byunghak Cho, Kunal Godbole, Ronghua Ni

Publikováno v: IEEE Journal of Solid-State Circuits. 54:1254-1265

An analog fractional- $N$ sampling phase-locked loop (PLL) is presented. It achieves 75-fs rms jitter, integrated from 10 kHz to 10 MHz, and a −249.7-dB figure of merit (FoM) at the fractional- $N$ mode with a 52-MHz reference clock. The measured f

Externí odkaz: https://explore.openaire.eu/search/publication?articleId=doi_________::6cadde0fbcc9502dc1b149e80cb00f45
https://doi.org/10.1109/jssc.2019.2899726

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A 5.5-7.3 GHz Analog Fractional-N Sampling PLL in 28-nm CMOS with 75 fsrmsJitter and −249.7 dB FoM

Autor: Chih-Wei Yao, Sang Won Son, Thomas Byunghak Cho, Ashutosh Verma, Yongrong Zuo, Kunal Godbole, Ivan Siu-Chuang Lu, Yongping Han, Pei-Yuan Chiang, Ronghua Ni, Wanghua Wu

Publikováno v: 2018 IEEE Radio Frequency Integrated Circuits Symposium (RFIC).

We present a low jitter, DTC-based analog fractional-N PLL with novel, background DTC gain calibration and reference clock duty cycle correction for high performance applications. The PLL achieves a 75-fs rms jitter, integrated from 10 kHz to 10 MHz

Externí odkaz: https://explore.openaire.eu/search/publication?articleId=doi_________::50bb1e7db04a82ec8b4c58e0c12e913c
https://doi.org/10.1109/rfic.2018.8428844

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