Zobrazeno 1 - 10
of 17
pro vyhledávání: '"Kun-Yung Ken Chang"'
Autor:
Jae Wook Kim, Chuen-huei Adam Chou, Kee Hian Tan, Kun-Yung Ken Chang, Adebabay M. Bekele, Yohan Frans, H. Ahn, Ilias Chlis, Yipeng Wang, Arianne Roldan, David Mahashin, H.-W. Hung, Stanley Chen, Lei Zhou, Declan Carey, Hongtao Zhang, Ronan Casey, Jay Im, Ying Cao, Winson Lin, Kevin Zheng
Publikováno v:
IEEE Journal of Solid-State Circuits. 56:7-18
A 36-way time-interleaved 56-GS/s 7-bit ADC is designed to realize 112-Gb/s pulse-amplitude modulation (PAM-4) transceiver in a 7-nm FinFET CMOS. The receiver analog front-end stages and the ADC track-and-hold (T/H) buffers are implemented using inve
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::9d4a37bd68a77c15acd26014ce64d6ef
https://doi.org/10.1109/jssc.2020.3024261
https://doi.org/10.1109/jssc.2020.3024261
Autor:
Wendemagegnehu T. Beyene, Xingchao Yuan, Phuong Le, Kambiz Kaviani, Kun-Yung Ken Chang, Amir Amirkhany, K. Sano, V. I. Murugan, Chaofeng Huang, Chris Madden, Keisuke Saito
Publikováno v:
IEEE Journal of Solid-State Circuits. 48:636-648
This paper describes a low-power receiver front-end in a bidirectional near-ground source-series terminated (SST) interface implemented in a 40-nm CMOS process, which supports low-common mode differential NRZ signaling up to 16-Gb/s data rates. The h
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::e54e65ae3ef7de961175064d228beb6e
https://doi.org/10.1109/jssc.2013.2242714
https://doi.org/10.1109/jssc.2013.2242714
Autor:
Manish Jain, C. Huang, Keisuke Saito, Wendemagegnehu T. Beyene, Kun-Yung Ken Chang, J. Wei, Deborah Dressier, T. J. Chin, Catherine Chen, Dave Secker, Phuong Le, Vijay Gadde, Chris Madden, Xingchao Yuan, Ting Wu, Chanh Tran, Mahabaleshwara, Sanku Mukherjee, Navin Kumar Mishra, Ling Yang, Leneesh Raghavan, Arul Sendhil, Amir Amirkhany, Hai Lan, Arun Vaidyanath, R. Schmitt, Gundlapalli Shanmukha Srinivas, Shuaeb Fazeel, Mohammad Hekmat, Kambiz Kaviani, Kapil Vyas, Jie Shen
Publikováno v:
IEEE Journal of Solid-State Circuits. 47:911-925
This paper presents a tri-modal asymmetric memory controller interface that achieves 12.8-Gbps single-ended (SE) signaling over 3" stripline FR4 traces. The controller can be configured to communicate with commercially available GDDR5 and DDR3 memori
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::421978d9bf7442239b44035690fb198d
https://doi.org/10.1109/jssc.2012.2185369
https://doi.org/10.1109/jssc.2012.2185369
Autor:
Ting Wu, Amir Amirkhany, Gundlapalli Shanmukha Srinivas, Norman Chan, J. Wei, Phuong Le, Mahabaleshwara, Kun-Yung Ken Chang, S. Fazeel, Wendemagegnehu T. Beyene, Chanh Tran, Keisuke Saito, K. Vyas, Vijay Gadde, Xudong Shi, Catherine Chen, Dave Secker, E. Ho, Mohammad Hekmat, Chris Madden, T. J. Chin, Navin Kumar Mishra, Manish Jain, Bing Ren Chuang, Chintan Thakkar, Arun Vaidyanath, R. Schmitt, Xingchao Yuan, Deborah Dressler, Jie Shen, S. Zhang, Chaofeng Huang, Kambiz Kaviani, Leneesh Raghavan
Publikováno v:
IEEE Journal of Solid-State Circuits. 47:926-937
This paper describes a tri-modal asymmetric bidirectional differential memory interface that supports data rates of up to 20 Gbps over 3" FR4 PCB channels while achieving power efficiency of 6.1 mW/Gbps at full speed. The interface also accommodates
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::303e64a359e3b0c8f35d9e990c5ad0e1
https://doi.org/10.1109/jssc.2012.2185370
https://doi.org/10.1109/jssc.2012.2185370
Autor:
Nhat Nguyen, Hae-Chang Lee, Reza Navid, Kun-Yung Ken Chang, Ting Wu, Jung-Hoon Chun, Brian S. Leibowitz, Fariborz Assaderaghi, Xudong Shi, Simon Li, Yohan Frans, F.S. Lee, Marko Aleksic, Richard E. Perego, Jared L. Zerbe, Kambiz Kaviani, Jie Shen, F. Quan, Wendemagegnehu T. Beyene, T. J. Chin
Publikováno v:
IEEE Journal of Solid-State Circuits. 44:1235-1247
This paper describes a bidirectional, differential, 16 Gb/s per link memory interface that includes a Controller and an emulated DRAM physical interface (PHY) designed in 65 nm CMOS. To achieve high data rate, the interface employs the following tech
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::8cc299ee9bdc3f35aad929e189a7ade4
https://doi.org/10.1109/jssc.2009.2014199
https://doi.org/10.1109/jssc.2009.2014199
Publikováno v:
IEEE Journal of Solid-State Circuits. 41:413-424
Supply-regulated phase-locked loops rely upon the VCO voltage regulator to maintain a low sensitivity to supply noise and hence low overall jitter. By analyzing regulator supply rejection, we show that in order to simultaneously meet the bandwidth an
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::85555486ac17217f5fed94ca059d5a60
https://doi.org/10.1109/jssc.2005.862347
https://doi.org/10.1109/jssc.2005.862347
Autor:
Yingxuan Li, Mark Horowitz, C. Huang, Kevin S. Donnelly, Kun-Yung Ken Chang, J. Wei, Stefanos Sidiropoulos, Simon Li
Publikováno v:
IEEE Journal of Solid-State Circuits. 38:747-754
This paper describes the design and implementation of a quad high-speed transceiver cell fabricated in 0.13-/spl mu/m CMOS technology. The clocking circuit of the cell employs a dual-loop architecture with a high-bandwidth core phase-locked loop (PLL
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::9fc696039e23096c90ad862678c33619
https://doi.org/10.1109/jssc.2003.810045
https://doi.org/10.1109/jssc.2003.810045
Autor:
T. J. Chin, Ting Wu, Richard E. Perego, Jung-Hoon Chun, Brian S. Leibowitz, Xudong Shi, Kambiz Kaviani, Hae-Chang Lee, Wendemagegnehu T. Beyene, Jie Shen, Kun-Yung Ken Chang
Publikováno v:
2008 IEEE Asian Solid-State Circuits Conference.
A transceiver for a memory controller operating at 16 Gb/s per link is implemented in 65 nm CMOS process. Timing calibration, equalization and diagnostic circuits for both memory read and write are on the controller to optimize the overall system per
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::e7e36f6ff4393654d3ce887f50bd3c3b
https://doi.org/10.1109/asscc.2008.4708720
https://doi.org/10.1109/asscc.2008.4708720
Autor:
Kun-Yung Ken Chang, T.J. Chin, Jung-Hoon Chun, Richard E. Perego, Hae-Chang Lee, Xudong Shi, Kambiz Kaviani, Jie Shen, Ting Wu
Publikováno v:
CICC
8 GHz clocking circuits for a 16 Gb/s/pin asymmetric memory interface [1] are described. A combination of an LC-PLL and a ring-PLL achieves improved jitter performance for multiple phase outputs with a wide frequency range. A direct phase mixer and a
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::c12d0c1c11922ec65717672f23a3d50d
https://doi.org/10.1109/cicc.2008.4672114
https://doi.org/10.1109/cicc.2008.4672114
Publikováno v:
1999 Symposium on VLSI Circuits. Digest of Papers (IEEE Cat. No.99CH36326).
A 32/spl times/32 synchronous crossbar chip was designed in a 0.27 /spl mu/m CMOS technology for use in a high-speed network switch. The crossbar chip uses 32 Asymmetric Serial Links to achieve high speed at the interfaces and to reduce both power an
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::b4c32e4af53755397a37effc966afbb0
https://doi.org/10.1109/vlsic.1999.797221
https://doi.org/10.1109/vlsic.1999.797221