Zobrazeno 1 - 10
of 11
pro vyhledávání: '"Kun-Ho Kwak"'
Publikováno v:
IEEE Transactions on Electron Devices. 57:474-481
For the first time, the smallest 3-D stacked six-transistor (6T) static-random-access-memory (SRAM) cell technology is successfully developed by using a laser crystallization process to grow perfect single-crystal Si layers on the amorphous dielectri
Autor:
Byoungkeun Son, Han-Byung Park, Hoon Lim, Jonghoon Na, Changmin Hong, Kun-Ho Kwak, Soon-Moon Jung, Kinam Kim, Jae-Joo Shim, Chadong Yeo
Publikováno v:
2007 IEEE Symposium on VLSI Technology.
Highly cost effective and high speed 72M bit density S3 SRAM technology was successfully achieved for standalone memory and embedded memory with selective epitaxial growth of Si films, low thermal SSTFT process , periphery only Co salicidation, and W
Autor:
Jae-Hoon Jang, Byung-Il Ryu, Hoosung Cho, Sung-Jin Kim, Kinam Kim, Jonghoon Na, Bonghyun Choi, Chadong Yeo, Yongha Kang, Dae-Gi Bae, Young-Chul Chang, Kun-Ho Kwak, Soon-Moon Jung, Jae-Hun Jeong, Hoon Lim, Jong-Hyuk Kim, Wonseok Cho
Publikováno v:
IEDM Technical Digest. IEEE International Electron Devices Meeting, 2004..
For the first time, the highest density SRAM, such as 512M bit SRAM, is developed by implementing the smallest 25F/sup 2/S/sup 3/ SRAM cell technology, whose cell size is 0.16/spl mu/m/sup 2/, and area saving peripheral SSTFT (stacked single-crystal
Autor:
Bonghyun Choi, J.H. Moon, Hoon Lim, Kun-Ho Kwak, B.J. Hwang, Y.H. Kang, Wonseok Cho, Sungjee Kim, Jae-Hun Jeong, W.R. Jung, Chadong Yeo, Keunwoo Kim, Ji-Hoon Kim, Jonghoon Na, Soon Moon Jung, J.H. Jang
Publikováno v:
2004 IEEE International SOI Conference (IEEE Cat. No.04CH37573).
The PMOS SSTFT (stacked single-crystal thin film transistor) is developed for achieving the smallest SRAM cell size, such as 45F/sup 2/, and low power mobile applications with the single crystallization technology of the Si thin films on the insulato
Autor:
Wonseok Cho, Kinam Kim, Jong-Hyuk Kim, Jae Hoon Jeong, Bonghyun Choi, Joo Young Kim, Jae-Joo Shim, Sunghyun Kwon, Soon-Moon Jung, Kun-Ho Kwak, Hoon Lim, Hoosung Cho, Changmin Hong, Jin-Ho Kim
Publikováno v:
Extended Abstracts of the 2005 International Conference on Solid State Devices and Materials.
Autor:
Byeong-In Choi, B.J. Hwang, Ji-Hyun Jeong, Y.H. Kang, Hoon Lim, J.H. Moon, Suk-Joon Kim, J.H. Jang, Je-Yoon Kim, Kinam Kim, Jonghoon Na, Jung Won-Joo, Wonsuk Cho, Kun-Ho Kwak, Seok-Min Jung, Chadong Yeo
Publikováno v:
Proceedings of the 30th European Solid-State Circuits Conference (IEEE Cat. No.04EX850).
We have realized a 46F/sup 2/ SRAM cell size of 0.294 /spl mu/m/sup 2/ with 80 nm technology and single stack S/sup 3/ cell technology. SSTFTs and vertical node contacts are major keys in the S/sup 3/ cell technology. The stacked single crystal silic
Autor:
Sunae Seo, Hyung-Guel Kim, Kun-Ho Kwak, Duk-ha Park, B.J. Hwang, Yang-Soo Son, K.N. Kim, Kyoung-Min Koh, J.H. Jang, J.Y. Lee
Publikováno v:
2003 International Symposium on VLSI Technology, Systems and Applications. Proceedings of Technical Papers. (IEEE Cat. No.03TH8672).
As scaling down the device, it is difficult to control the standby leakage and device performance at the same time. In this work, 6-transistor SRAM cell using buried channel PMOS technology was introduced and the device for low power consumption was
Autor:
Kinam Kim, J.H. Jang, Hyung-Guel Kim, Kyoung-Min Koh, D. Park, Kun-Ho Kwak, Yang-Soo Son, G.H. Han, B.J. Hwang
Publikováno v:
2003 Symposium on VLSI Technology. Digest of Technical Papers (IEEE Cat. No.03CH37407).
High speed and ultra-low power SRAM using single gate CMOS technology was developed. The drive currents of NMOSFET and PMOSFET were 410 /spl mu/A//spl mu/m and 205 /spl mu/A//spl mu/m, respectively. The random access time of 17 ns at 1.65 V operation
Autor:
Byeong-In Choi, Kinam Kim, Kun-Ho Kwak, Wonsuk Cho, J.H. Jang, Ji-Hyun Jeong, Suk-Joon Kim, Y.H. Kang, Jonghoon Na, Jung Won-Joo, Ji Hye Moon, Hyung-Chul Lim, Seok-Min Jung, Chadong Yeo, Jun-Sang Kim, B.J. Hwang
Publikováno v:
Extended Abstracts of the 2004 International Conference on Solid State Devices and Materials.
Autor:
Jae-Hun Jeong, Wonseok Cho, Kun-Ho Kwak, Hoon Lim, Bonghyun Choi, Jae-Hoon Jang, Byung-Jun Hwang, Jong-Hyuk Kim, Jaehwan Moon, Soon-Moon Jung, Kinam Kim
Publikováno v:
Digest of Technical Papers. 2004 Symposium on VLSI Technology, 2004..
The smallest 25F/sup 2/ SRAM cell size of 0.16um/sup 2/ is realized by S/sup 3/ cell technology and SSTFT with 193nm ArF lithography process. The stacked single-crystal thin film is developed and used for the first time in the SRAM cell to make the S