Zobrazeno 1 - 7
of 7
pro vyhledávání: '"Kuei-Shun Chen"'
Autor:
B.F. Wu, C.O. Chui, Matt Yeh, Shun‐yu Wang, K.C. Kwong, R. Chen, Jen-Hsiang Lu, Sy Wu, C.H. Chang, Kenlin Huang, Vincent S. Chang, Kuei-Shun Chen, W.H. Wu, C.H. Chen, J.Y. Yeh, B.C. Hsu
Publikováno v:
2020 IEEE Symposium on VLSI Technology.
For the first time, multiple-Vt (multi-Vt) device options with Vt range> 250 mV are achieved in standard cells at dimensions beyond 7nm technology node. To overcome the common scaling challenges of potential device options such as FinFET and gate all
Autor:
C.Y. Lee, M.C. Chiang, Lin Chih-Yung, Kuei-Shun Chen, V.S. Chang, C.H. Yao, R. Chen, S.M. Jang, R.F. Tsui, C.H. Chang, Y.K. Wu, C.H. Tsai, T. Miyashita, Jhon-Jhy Liaw, Huicheng Chang, Shien-Yang Wu, Joy Cheng, K.H. Pan, Chang-Ta Yang, C. H. Hsieh, Kai-Yuan Ting, Y. Ku
Publikováno v:
2016 IEEE Symposium on VLSI Technology.
For the first time, we demonstrate the smallest, fully functional 32Mb 6-T high density SRAM reported in literature with scaled bulk FinFETs for CMOS technology beyond 10nm node. Scaled FinFET devices exhibit excellent electrostatic with DIBL of
Autor:
Lin Chih-Yung, Tze-Liang Lee, S.Y. Chang, R.F. Tsui, Ming-Huan Tsai, K.H. Pan, Joy Cheng, R. Chen, Kuei-Shun Chen, C.H. Yao, T. Yamamoto, M.C. Chiang, Y.K. Wu, T. Chang, Kai-Yuan Ting, J.H. Chen, Jhon-Jhy Liaw, S. M. Jang, C. H. Lee, S.H. Yang, Y. Ku, H. M. Lee, Vincent S. Chang, Hou-Yu Chen, Liang Min-Chang, H.T. Huang, S.Z. Chang, Yuan-Hung Chiu, Shien-Yang Wu, W. Chang, Chun-Kuang Chen, C.H. Tsai, T. Miyashita, C.H. Chang
Publikováno v:
2014 IEEE International Electron Devices Meeting.
Advancing the state-of-the-art 16nm technology reported last year, an enhanced 16nm CMOS technology featuring the second generation FinFET transistors and advanced Cu/low-k interconnect is presented. Core devices are re-optimized to provide additiona
Autor:
Y. Ku, Y.K. Wu, C.H. Tsai, Tze-Liang Lee, K.H. Pan, T. Miyashita, C.H. Chang, Kuei-Shun Chen, C.H. Yao, Chun-Kuang Chen, C. C. Kuo, S.H. Yang, Jhon-Jhy Liaw, S. M. Jang, Hou-Yu Chen, Liang Min-Chang, W. Chang, H. Y. Chen, R. Chen, H. T. Lin, Chang Chih-Yang, H. M. Lee, Ming-Huan Tsai, M. Yeh, H. M. Lien, H. C. Huang, B. C. Hsu, Joy Cheng, Y. H. Chen, T. Yamamoto, M.C. Chiang, C. C. Liu, J.H. Chen, Yuan-Hung Chiu, Shien-Yang Wu, Y. C. Lu, R.F. Tsui, Lin Chih-Yung, T. Chang, S.Y. Chang, Kai-Yuan Ting, P. R. Chang, Vincent S. Chang
Publikováno v:
2013 IEEE International Electron Devices Meeting.
For the first time, we present a state-of-the-art energy-efficient 16nm technology integrated with FinFET transistors, 0.07um2 high density (HD) SRAM, Cu/low-k interconnect and high density MiM for mobile SoC and computing applications. This technolo
Autor:
C.H. Lee, Y.T. Hou, Carlos H. Diaz, T.T. Chu, Kuei-Shun Chen, K.S. You, K.B. Thei, Joy Cheng, W.T. Lu, J.A. Ng, C.J. Chen, L.Y. Yeh, C.L. Chen, Y. Ku, Yu. Yasuda, K. Goto, S.H. Yang, K.C. Lin, H. Chuang, W.C. Yang, M.H. Yu, P.F. Hsu, Y.S. Chao, H.T. Huang, Chun-Kuang Chen, Liang Min-Chang, C.P. Tsao, K.T. Huang, Y.H. Peng, Vincent S. Chang, C.H. Chen, Jhon-Jhy Liaw, S. M. Jang
Publikováno v:
2008 IEEE International Electron Devices Meeting.
A 32 nm gate-first high-k/metal-gate technology is demonstrated with the strongest performance reported to date to the best of our knowledge. Drive currents of 1340/940 muA/mum (n/p) are achieved at Ioff=100 nA/mum, Vdd=1 V, 30 nm physical gate lengt
Autor:
Kuei-Shun Chen, Wen-Chuan Wang, Sheng-Chi Chin, Hsin-Chang Lee, Chi-Lun Lu, Yao Ching Ku, Ru-Gun Liu, Chih-Cheng C. Chin, Ren-Guey Hsieh, Hung-Chang Hsieh, John Lin, Shih-Ming Chang, Cherng-Shyan Tsay, Yung-Sung Yen
Publikováno v:
SPIE Proceedings.
The control of global critical dimension uniformity (GCDU) across the entire mask becomes an important factor for the high-end masks quality. Three major proceses induce GCDU error before after-developing inspection (ADI) including the E-Beam writing
Autor:
Jaw-Jung Shin, Fu-Jye Liang, Ming Lu, Li-Wei Kung, Fu-Liang Yang, Chien-Chao Huang, Hsun-Chih Tsao, Cheng-Kuo Wen, Jhon-Jhy Liaw, Ke-Wei Su, Yu-Jun Chou, Yi-Chun Huang, Yung-Shun Chen, Di-Hong Lee, Tze-Liang Lee, Shui-Ming Cheng, Samuel Fung, Chenming Hu, Bin-Chang Chang, Tang-Xuan Chung, Chuan-Ping Hou, Chang-Yun Chang, Tsai-Sheng Gau, Kuang-Hsin Chen, J.Y.-C. Sun, Cheng Chuan Huang, Hou-Yu Chen, Jan-Wen You, Liang Min-Chang, Jhi-cheng Lu, Chi-Chun Chen, Burn-Jeng Lin, Kuei-Shun Chen, Yee-Chia Yeo, Han-Jan Tao, J.H. Chen, Shih-Chang Chen, Hung-Wei Chen, Carlos H. Diaz, Yi-Ming Sheu, Chun-Kuang Chen, Bor-Wen Chan, Ying-Ho Chen, W. Chang, King-Chang Shu, C.H. Chen, Chii-Ming Wu, Cheng-hung Chang
Publikováno v:
Scopus-Elsevier
A 65 nm node strained SOI technology with high performance is demonstrated, providing drive currents of 1015 and 500 /spl mu/A//spl mu/m for N-FET and P-FET, respectively, at an off-state leakage of 40 nA//spl mu/m using 1 V operation. The technology
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_dedup___::d2cd43133598ebbb8ca11a12eccb16a1
http://www.scopus.com/inward/record.url?eid=2-s2.0-17644444298&partnerID=MN8TOARS
http://www.scopus.com/inward/record.url?eid=2-s2.0-17644444298&partnerID=MN8TOARS