Zobrazeno 1 - 10
of 23
pro vyhledávání: '"Kuei-Jyun Chen"'
Autor:
Yu-Ting Huang, Shen-Li Chen, Jia Ming Lin, Yi Cih Wu, Chih Ying Yen, Kuei Jyun Chen, Chih Hung Yang
Publikováno v:
Applied Mechanics and Materials. 870:401-406
Electrostatic-discharge (ESD) immunity measurements of different layout manners in the drain-side of HV pLDMOS devices are investigated in this paper. Here, eleven kinds of drain-side "npnpn" arranged-types of pLDMOS-SCR parasitic structure are used
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::d4db724979f9a525d2dbce0551554265
https://doi.org/10.4028/www.scientific.net/amm.870.401
https://doi.org/10.4028/www.scientific.net/amm.870.401
Autor:
Yu-Lin Lin, Jia-Ming Lin, Yi-Hao Chiu, Yi-Hao Chao, Chih-Hung Yang, Yi-Cih Wu, Kuei-Jyun Chen, Jen-Hao Lo, Chun-Ting Kuo, Chih-Ying Yen, Hung-Wei Chen, Shen-Li Chen
Publikováno v:
2017 IEEE 24th International Symposium on the Physical and Failure Analysis of Integrated Circuits (IPFA).
In this work, ESD immunity enhancement for the HV n-channel LDMOS with source-end discrete islands fabricated by a TSMC 0.25 μm 60 V process was investigated. An nLDMOS device always has poor ESD capability. If discrete n+ islands are formed in the
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::2e5ff794c7525fb8013d9c1147a6f845
https://doi.org/10.1109/ipfa.2017.8060126
https://doi.org/10.1109/ipfa.2017.8060126
Autor:
Yi-Hao Chao, Kuei-Jyun Chen, Jen-Hao Lo, Chih-Ying Yen, Yi-Cih Wu, Shen-Li Chen, Jia-Ming Lin, Yu-Lin Lin, Yi-Hao Chiu, Chih-Hung Yang, Chun-Ting Kuo
Publikováno v:
2017 IEEE 3rd International Future Energy Electronics Conference and ECCE Asia (IFEEC 2017 - ECCE Asia).
HV n-/p-LDMOS devices with the source-side extending into bulk-region to evaluate the electrostatic-discharge (ESD) protection robustness by a TSMC 0.25 µm 60 V process are investigated in this paper. After a systematic analysis, the trigger voltage
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::200d5a2bdf4d88ca1f7b3656918f983b
https://doi.org/10.1109/ifeec.2017.7992390
https://doi.org/10.1109/ifeec.2017.7992390
Autor:
Yi-Cih Wu, Yi-Hao Chiu, Jia-Ming Lin, Chih-Ying Yen, Yi-Hao Chao, Chih-Hung Yang, Kuei-Jyun Chen, Chun-Ting Kuo, Yu-Lin Lin, Hung-Wei Chen, Jen-Hao Lo, Shen-Li Chen
Publikováno v:
2017 IEEE International Conference on Consumer Electronics - Taiwan (ICCE-TW).
The pLDMOS related devices fabricated by a TSMC 0.25 µm 60 V process was investigated in this paper. For the ESD improvement, some DUTs inserting the N+ zone to form an embedded SCR in the drain end or guard-ring area, respectively. From the TLP tes
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::4a40b0b064bd57c928bba1c92d1cdfd9
https://doi.org/10.1109/icce-china.2017.7991155
https://doi.org/10.1109/icce-china.2017.7991155
Autor:
Shen-Li Chen, Chih-Ying Yen, Kuei-Jyun Chen, Hung-Wei Chen, Jia-Ming Lin, Yu-Lin Lin, Yi-Hao Chiu, Marty Lo, Jen-Hao Lo, Chih-Hung Yang, Chun-Ting Kuo, Yi-Hao Chao, Yi-Cih Wu, Dylan Chen
Publikováno v:
2017 6th International Symposium on Next Generation Electronics (ISNE).
The impacts of current-path variation on the ESD robustness of nLDMOS devices as the drain-side modulation by a 0.18 μm/40 V process are evaluated in this paper. From the transmission-line-pulsing (TLP) measurement, the secondary breakdown current (
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::0483dd37d3fdf4c5e2c292946dcb3e44
https://doi.org/10.1109/isne.2017.7968708
https://doi.org/10.1109/isne.2017.7968708
Autor:
YiCih Wu, Yi-Hao Chao, Yi-Hao Chiu, Chih-Ying Yen, Chih-Hung Yang, Kuei-Jyun Chen, Shen-Li Chen
Publikováno v:
Proceedings of the 2016 International Conference on Engineering and Advanced Technology.
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::a8deb797df189f85b5b18ce697089075
https://doi.org/10.2991/iceat-16.2017.41
https://doi.org/10.2991/iceat-16.2017.41
Autor:
Shen-Li Chen, Jia-Ming Lin, Chih-Ying Yen, Yu-Ting Huang, Kuei-Jyun Chen, Chih-Hung Yang, Yi-Cih Wu
Publikováno v:
2016 IEEE International Conference on Power and Energy (PECon).
In this paper, Electrostatic-Discharge (ESD) reliability study of 45-V HV pLDMOS devices with the source-side discrete islands is investigated. A pure pLDMOS transistor is always frail in ESD harms (I t2 = 0.107-A). However, if a pLDMOS device with t
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::f405f85375138d3698e03bfc460abdab
https://doi.org/10.1109/pecon.2016.7951535
https://doi.org/10.1109/pecon.2016.7951535
Autor:
Chih-Ying Yen, Jia-Ming Lin, Yi-Cih Wu, Shen-Li Chen, Yu-Ting Huang, Kuei-Jyun Chen, Chih-Hung Yang
Publikováno v:
GCCE
An evaluation of electrostatic-discharge (ESD) reliability by changing the source-end layout of 45-V HV pLDMOS devices is investigated in this paper. After testing and systematic analysis, it can be found that a traditional pLDMOS sample is always ve
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::21f08892a55ac1bafcc620ee4ef15c39
https://doi.org/10.1109/gcce.2016.7800464
https://doi.org/10.1109/gcce.2016.7800464
Publikováno v:
ICCE-TW
The electrostatic-discharge (ESD) protection capability of HV nLDMOS devices with the source-side engineering by a TSMC 0.25μm 60-V is investigated in this paper. It can be found that a pure nLDMOS device has a poor anti-ESD ability (It2 = 1.833A).
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::6e20a5c3c45b0f68a4219489a39aaf55
https://doi.org/10.1109/icce-tw.2016.7521041
https://doi.org/10.1109/icce-tw.2016.7521041
Autor:
Chih-Ying Yen, Jia-Ming Lin, Kuei-Jyun Chen, Yi-Cih Wu, Chih-Hung Yang, Hung-Wei Chen, Shen-Li Chen
Publikováno v:
2016 IEEE 8th International Power Electronics and Motion Control Conference (IPEMC-ECCE Asia).
In this paper, the electrostatic-discharge (ESD) robustness improvement by modulating the drain-side embedded SCR of an HV nLDMOS device is investigated via a TSMC 0.25 µm 60 V process. After a systematic layout design and data analysis, it can be f
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::910e63c12ac26c9ee4585f3e4b7f8265
https://doi.org/10.1109/ipemc.2016.7512534
https://doi.org/10.1109/ipemc.2016.7512534