Zobrazeno 1 - 10
of 11
pro vyhledávání: '"Kshitij Sudan"'
Publikováno v:
IEEE Transactions on Computers. 61:1697-1710
Moore's Law improvement in transistor density is driving a rapid increase in the number of cores per processor. DRAM device capacity and energy efficiency are increasing at a slower pace, so the importance of DRAM power is increasing. This problem pr
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::e4c01cc34ca5c1f9245415d57928ccd0
https://doi.org/10.1109/tc.2012.119
https://doi.org/10.1109/tc.2012.119
Publikováno v:
International Journal of Parallel Programming. 40:57-83
Modern processors such as Tilera’s Tile64, Intel’s Nehalem, and AMD’s Opteron are migrating memory controllers (MCs) on-chip, while maintaining a large, flat memory address space. This trend to utilize multiple MCs will likely continue and a co
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::e8b25e90f7ab8750bfd7b395c7d4afb0
https://doi.org/10.1007/s10766-011-0178-1
https://doi.org/10.1007/s10766-011-0178-1
Autor:
David Nellans, Al Davis, Kshitij Sudan, Manu Awasthi, Rajeev Balasubramonian, Niladrish Chatterjee
Publikováno v:
ASPLOS
Power consumption and DRAM latencies are serious concerns in modern chip-multiprocessor (CMP or multi-core) based compute systems. The management of the DRAM row buffer can significantly impact both power consumption and latency. Modern DRAM systems
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_dedup___::1e053ddabc7d88fd003ddabf396e27ed
https://doi.org/10.1145/1735970.1736045
https://doi.org/10.1145/1735970.1736045
Autor:
Min Xu, G. Lauterbach, Kshitij Sudan, D. Mallick, Saisanthosh Balakrishnan, S. Lie, Rajeev Balasubramonian
Publikováno v:
HPCA
Large web-scale applications typically use a distributed platform, like clusters of commodity servers, to achieve scalable and low-cost processing. The Map-Reduce framework and its open-source implementation, Hadoop, is commonly used to program these
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::a6553c958d1ad48dc99bf0e1db949e08
https://doi.org/10.1109/hpca.2013.6522316
https://doi.org/10.1109/hpca.2013.6522316
Publikováno v:
PACT
Co-location of applications is a proven technique to improve hardware utilization. Recent advances in virtualization have made co-location of independent applications on shared hardware a common scenario in datacenters. Co-location, while maintaining
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::1cc0441dcb4fa09576b6a1082e0ffa53
https://doi.org/10.1145/2370816.2370834
https://doi.org/10.1145/2370816.2370834
Autor:
Manu Awasthi, Viii Srinivasan, Manjunath Shevgoor, Bipin Rajendran, Kshitij Sudan, Rajeev Balasubramonian
Publikováno v:
HPCA
Many memory cell technologies are being considered as possible replacements for DRAM and Flash technologies, both of which are nearing their scaling limits. While these new cells (PCM, STT-RAM, FeRAM, etc.) promise high density, better scaling, and n
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::42c29e5520231de6d4cb53d44e7b4b29
https://doi.org/10.1109/hpca.2012.6168941
https://doi.org/10.1109/hpca.2012.6168941
Publikováno v:
PACT
Future scalable multi-core chips are expected to implement a shared last-level cache (LLC) with banks distributed on chip, forcing a core to incur non-uniform access latencies to each bank. Consequently, high performance and energy efficiency depend
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::67dfb530207944272b64f421208624eb
https://doi.org/10.1109/pact.2011.26
https://doi.org/10.1109/pact.2011.26
Publikováno v:
Computer Architecture ISBN: 9783642243219
ISCA Workshops
ISCA Workshops
Modern and future server-class processors will incorporate many cores. Some studies have suggested that it may be worthwhile to dedicate some of the many cores for specific tasks such as operating system execution. OS off-loading has two main benefit
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_dedup___::f1da833b685a414a6aa06cc1091951a3
https://doi.org/10.1007/978-3-642-24322-6_23
https://doi.org/10.1007/978-3-642-24322-6_23
Publikováno v:
PACT
Modern processors such as Tilera's Tile64, Intel's Nehalem, and AMD's Opteron are migrating memory controllers (MCs) on-chip, while maintaining a large, flat memory address space. This trend to utilize multiple MC's will likely continue and a core or
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::6bfed395b1934d2b616388a107684d80
https://doi.org/10.1145/1854273.1854314
https://doi.org/10.1145/1854273.1854314
Publikováno v:
ISPASS
In the past ten years, computer architecture has seen a paradigm shift from emphasizing single thread performance to energy efficient, throughput oriented, chip multiprocessors. Several studies have suggested that it may be worthwhile to off-load exe
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::c22c74051f6a50c1e2e413009b8437c1
https://doi.org/10.1109/ispass.2010.5452057
https://doi.org/10.1109/ispass.2010.5452057