Výsledky vyhledávání - "Kristof Blutman"

Logic design partitioning for stacked power domains

Autor: Jiajia Li, Hamed Fatemi, Andrew B. Kahng, Ajay Kapoor, Kristof Blutman, Jose Pineda de Gyvez

Publikováno v: IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 25(11):7999260, 3045-3056. Institute of Electrical and Electronics Engineers

Energy and battery lifetime constraints are critical challenges to IC designs. Stacked power-domain implementation, which connects voltage domains in series, can effectively improve power delivery efficiency and thus improve battery lifetime. However

Externí odkaz: https://explore.openaire.eu/search/publication?articleId=doi_dedup___::e5617bc0c3607344b386863a8a59cb22
http://www.scopus.com/inward/record.url?scp=85028986368&partnerID=8YFLogxK

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A low-power microcontroller in a 40-nm CMOS using charge recycling

Autor: Juan Echeverri, Arnoud van der Wel, Leo Sevat, Hamed Fatemi, Kristof Blutman, Arjun Majumdar, Jose Pineda de Gyvez, Ajay Kapoor, Jacinto Garcia Martinez, Kofi A. A. Makinwa

Publikováno v: IEEE Journal of Solid State Circuits, 52(4)
IEEE Journal of Solid-State Circuits, 52(4):7815353, 950-960. Institute of Electrical and Electronics Engineers

A 40-nm microcontroller featuring voltage stacked memory and logic is presented. This involved connecting the power domains of the memory and logic in series, such that the ground of one power domain is connected to the positive supply rail of the ot

Externí odkaz: https://explore.openaire.eu/search/publication?articleId=doi_dedup___::9d152fede8aeb02113e434c91ccbb607
http://www.scopus.com/inward/record.url?scp=85009872709&partnerID=8YFLogxK

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Floorplan and placement methodology for improved energy reduction in stacked power-domain design

Autor: Jiajia Li, Ajay Kapoor, Jose Pineda de Gyvez, Andrew B. Kahng, Hamed Fatemi, Kristof Blutman

Publikováno v: 2017 22nd Asia and South Pacific Design Automation Conference, ASP-DAC 2017, 444-449
STARTPAGE=444;ENDPAGE=449;TITLE=2017 22nd Asia and South Pacific Design Automation Conference, ASP-DAC 2017
ASP-DAC

Energy and battery lifetime constraints are critical challenges to IC designs. Stacked power-domain implementation, which stacks voltage domains in a design, can effectively improve the power delivery efficiency and thus improve battery lifetime. How

Externí odkaz: https://explore.openaire.eu/search/publication?articleId=doi_dedup___::f750a6d21e8c96b7935bfe686837cc4f
https://doi.org/10.1109/aspdac.2017.7858363

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A microcontroller with 96% power-conversion efficiency using stacked voltage domains

Autor: Jacinto Garcia Martinez, Arjun Majumdar, Kofi A. A. Makinwa, Kristof Blutman, Ajay Kapoor, Leo Sevat, Juan Echeverri, Hamed Fatemi, Arnoud van der Wel, Jose Pineda de Gyvez

Publikováno v: 2016 IEEE Symposium on VLSI Circuits, 15-17 June 2016, Honolulu, Hawaii, 1-2
STARTPAGE=1;ENDPAGE=2;TITLE=2016 IEEE Symposium on VLSI Circuits, 15-17 June 2016, Honolulu, Hawaii
VLSI Circuits

This paper presents a CMOS 40nm microcontroller where for the first time, stacked voltage domains are used. The system features an ARM Cortex M0+ processor, 4kB ROM, 16kB SRAM, peripherals, and an on-chip switched-capacitor voltage regulator (SCVR).

Externí odkaz: https://explore.openaire.eu/search/publication?articleId=doi_dedup___::97e334d0dc3d5e749730aa0724bfb3cd
https://research.tue.nl/nl/publications/8bb88168-41ca-47a6-9a24-603573b3b071

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Lower power by voltage stacking

Autor: Hamed Fatemi, Jose Pineda de Gyvez, Ajay Kapoor, Kristof Blutman, Jacinto Garcia Martinez

Publikováno v: Proceedings of the 53rd Annual Design Automation Conference, DAC 2016, 5-9 June 2016, Austin, Texas, 1-5
STARTPAGE=1;ENDPAGE=5;TITLE=Proceedings of the 53rd Annual Design Automation Conference, DAC 2016, 5-9 June 2016, Austin, Texas
DAC

Stacking voltage domains on top of each other is a design approach that is getting the attention of engineering communities due to the implicit high efficiency of the power delivery. Previous works have shown voltage stacking at the core level only.

Externí odkaz: https://explore.openaire.eu/search/publication?articleId=doi_dedup___::4f9ef39d4810bd512d068c4bc43b6fc0
https://doi.org/10.1145/2897937.2898041

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A 0.1pJ Freeze Vernier time-to-digital converter in 65nm CMOS

Autor: Nick van der Meijs, Amir Zjajo, Kristof Blutman, Jan A. Angevare

Publikováno v: ISCAS

A Freeze Vernier delay line time-to-digital converter for very low power and high resolution is presented. The Freeze Vernier Delay Line is a Vernier-type TDC, where the state of the start line can be frozen by the stop line, omitting the power-hungr

Externí odkaz: https://explore.openaire.eu/search/publication?articleId=doi_________::e506a615ba40a45f6abff17b4b48baf7
https://doi.org/10.1109/iscas.2014.6865071

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A CMOS 0.23pj Freeze Vernier Time-To-Digital Converter

Autor: Amir Zjajo, Nick van der Meijs, Kristof Blutman, Jan A. Angevare

Publikováno v: NORCHIP

A novel Time-to-Digital Converter architecture for high resolution and low power is proposed. The Freeze Vernier Delay Line is a Vernier-type TDC, where the state of the slow delay line can be frozen by the fast delay line, omitting the power-hungry

Externí odkaz: https://explore.openaire.eu/search/publication?articleId=doi_________::0ddb0217e9e49860c93f0697387a6f27
https://doi.org/10.1109/norchip.2013.6702019

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