Accurate Energy Modelling on the Cortex-M0 Processor for Profiling and Static Analysis

Autor: Kris Nikov, Kyriakos Georgiou, Zbigniew Chamski, Kerstin Eder, Jose Nunez-Yanez

Publikováno v: Nikov, K, Georgiou, K, Chamski, Z, Eder, K & Nunez-Yanez, J 2023, Accurate Energy Modelling on the Cortex-M0 Processor for Profiling and Static Analysis . in 2022 29th IEEE International Conference on Electronics, Circuits and Systems (ICECS) . ICECS 2022-29th IEEE International Conference on Electronics, Circuits and Systems, Proceedings, Institute of Electrical and Electronics Engineers (IEEE), 29th IEEE International Conference on Electronics, Circuits and Systems, ICECS 2022, Glasgow, United Kingdom, 24/10/22 . https://doi.org/10.1109/ICECS202256217.2022.9971086

Energy modelling can enable energy-aware software development and assist the developer in meeting an application's energy budget. Although many energy models for embedded processors exist, most do not account for processor-specific configurations, ne

Externí odkaz: https://explore.openaire.eu/search/publication?articleId=doi_dedup___::af1b51321cfa5097efe2b693ffddb3e5
https://hdl.handle.net/1983/3624d288-c88a-4718-851e-ce0635283f63

Evaluation of Early-exit Strategies in Low-cost FPGA-based Binarized Neural Networks

Autor: Minxuan Kong, Kris Nikov, Jose Luis Nunez-Yanez

Publikováno v: 2022 25th Euromicro Conference on Digital System Design (DSD).

Externí odkaz: https://explore.openaire.eu/search/publication?articleId=doi_________::bb8e17b8e6b30e9611954eafb3490f85
https://doi.org/10.1109/dsd57027.2022.00035

Run-Time Power Modelling in Embedded GPUs with Dynamic Voltage and Frequency Scaling

Autor: Kris Nikov, Kerstin Eder, Mohammad Hosseinabady, Jose L Nunez-Yanez

Publikováno v: PARMA-DITAM@HiPEAC
Proceedings of the 11th Workshop on Parallel Programming and Run-Time Management Techniques for Many-core Architectures / 9th Workshop on Design Tools and Architectures for Multicore Embedded Computing Platforms

This paper investigates the application of a robust CPU-based power modelling methodology that performs an automatic search of explanatory events derived from performance counters to embedded GPUs. A 64-bit Tegra TX1 SoC is configured with DVFS enabl

Externí odkaz: https://explore.openaire.eu/search/publication?articleId=doi_dedup___::8f869bab1258d08899d1bc77c2abd042