Zobrazeno 1 - 10
of 197
pro vyhledávání: '"Koziris, Nectarios"'
Autor:
Papadopoulos, Nikolaos-Charalampos, Psomadakis, Stratos, Karakostas, Vasileios, Koziris, Nectarios, Pnevmatikatos, Dionisios N.
The RISC-V SVNAPOT Extension aims to remedy the performance overhead of the Memory Management Unit (MMU), under heavy memory loads. The Privileged Specification defines additional Natural-Power-of-Two (NAPOT) multiples of the 4KB base page size, with
Externí odkaz:
http://arxiv.org/abs/2406.17802
Autor:
Giannoula, Christina, Strati, Foteini, Siakavaras, Dimitrios, Goumas, Georgios, Koziris, Nectarios
Concurrent priority queues are widely used in important workloads, such as graph applications and discrete event simulations. However, designing scalable concurrent priority queues for NUMA architectures is challenging. Even though several NUMA-obliv
Externí odkaz:
http://arxiv.org/abs/2406.06900
Autor:
Mpakos, Panagiotis, Galanopoulos, Dimitrios, Anastasiadis, Petros, Papadopoulou, Nikela, Koziris, Nectarios, Goumas, Georgios
The SpMV kernel is characterized by high performance variation per input matrix and computing platform. While GPUs were considered State-of-the-Art for SpMV, with the emergence of advanced multicore CPUs and low-power FPGA accelerators, we need to re
Externí odkaz:
http://arxiv.org/abs/2302.04225
Autor:
Giannoula, Christina, Huang, Kailong, Tang, Jonathan, Koziris, Nectarios, Goumas, Georgios, Chishti, Zeshan, Vijaykumar, Nandita
Resource disaggregation offers a cost effective solution to resource scaling, utilization, and failure-handling in data centers by physically separating hardware devices in a server. Servers are architected as pools of processor, memory, and storage
Externí odkaz:
http://arxiv.org/abs/2301.09674
Autor:
Giannoula, Christina, Huang, Kailong, Tang, Jonathan, Koziris, Nectarios, Goumas, Georgios, Chishti, Zeshan, Vijaykumar, Nandita
Resource disaggregation offers a cost effective solution to resource scaling, utilization, and failure-handling in data centers by physically separating hardware devices in a server. Servers are architected as pools of processor, memory, and storage
Externí odkaz:
http://arxiv.org/abs/2301.00414
Autor:
Giannoula, Christina, Fernandez, Ivan, Gómez-Luna, Juan, Koziris, Nectarios, Goumas, Georgios, Mutlu, Onur
Several manufacturers have already started to commercialize near-bank Processing-In-Memory (PIM) architectures. Near-bank PIM architectures place simple cores close to DRAM banks and can yield significant performance and energy improvements in parall
Externí odkaz:
http://arxiv.org/abs/2204.00900
Autor:
Alexiou, Giorgos, Papastefanatos, George, Stamatopoulos, Vassilis, Koutrika, Georgia, Koziris, Nectarios
In this work, we explore the problem of correctly and efficiently answering complex SPJ queries issued directly on top of dirty data. We introduce QueryER, a framework that seamlessly integrates Entity Resolution into Query Processing. QueryER execut
Externí odkaz:
http://arxiv.org/abs/2202.01546
Autor:
Giannoula, Christina, Fernandez, Ivan, Gómez-Luna, Juan, Koziris, Nectarios, Goumas, Georgios, Mutlu, Onur
Several manufacturers have already started to commercialize near-bank Processing-In-Memory (PIM) architectures. Near-bank PIM architectures place simple cores close to DRAM banks and can yield significant performance and energy improvements in parall
Externí odkaz:
http://arxiv.org/abs/2201.05072
Autor:
Giannoula, Christina, Vijaykumar, Nandita, Papadopoulou, Nikela, Karakostas, Vasileios, Fernandez, Ivan, Gómez-Luna, Juan, Orosa, Lois, Koziris, Nectarios, Goumas, Georgios, Mutlu, Onur
Near-Data-Processing (NDP) architectures present a promising way to alleviate data movement costs and can provide significant performance and energy benefits to parallel applications. Typically, NDP architectures support several NDP units, each inclu
Externí odkaz:
http://arxiv.org/abs/2101.07557
Autor:
Papadopoulos, Nikolaos Charalampos, Karakostas, Vasileios, Nikas, Konstantinos, Koziris, Nectarios, Pnevmatikatos, Dionisios N.
The Rocket Chip Generator uses a collection of parameterized processor components to produce RISC-V-based SoCs. It is a powerful tool that can produce a wide variety of processor designs ranging from tiny embedded processors to complex multi-core sys
Externí odkaz:
http://arxiv.org/abs/2009.07723