Zobrazeno 1 - 9
of 9
pro vyhledávání: '"Kozaburo Kurita"'
Publikováno v:
IEEE Journal of Solid-State Circuits. 26:585-589
Described is a phase-locked loop (PLL)-based BiCMOS on-chip clock generator (PCG), which is used to generate an internal clock synchronized to a reference clock from outside the chip. In order to obtain a very wide operation bandwidth, it is proposed
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::426703440c619c5493761356dd409248
https://doi.org/10.1109/4.75059
https://doi.org/10.1109/4.75059
Publikováno v:
Electronics and Communications in Japan (Part II: Electronics). 72:1-9
To improve the speed of the processors for CPU of minicomputers and other systems, it is required to improve the machine cycle and the memory cycle, which are the performance indexes of the system. The general idea to realize a high-speed memory cycl
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::6018ff1366fa45b27ddd512ac31a7830
https://doi.org/10.1002/ecjb.4420720901
https://doi.org/10.1002/ecjb.4420720901
Autor:
Masahiro Iwamura, Tadaaki Bandoh, Hideo Maejima, S. Tanaka, Kozaburo Kurita, Atsuo Hotta, Tatsumi Yamauchi, Takashi Hotta
Publikováno v:
IEEE Journal of Solid-State Circuits. 23:500-506
The CMOS/bipolar standard cell library has been enhanced from 2 to 1.3 mu m for application to VLSI computers, such as 32-bit supermini- and microcomputers. This library has macrocells such as a 256-kb/8.4-ns ROM, 32-bit/4.5-ns carry propagation circ
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::59b0551304c432d9419026dbbd1f605b
https://doi.org/10.1109/4.1013
https://doi.org/10.1109/4.1013
Autor:
M. Ueno, Ikuro Masuda, Kozaburo Kurita, Hideo Maejima, Atsuo Hotta, Masahiro Iwamura, Takashi Hotta
Publikováno v:
IEEE Journal of Solid-State Circuits. 21:808-813
High-performance bipolar/CMOS (Hi-BiCMOS) technology, in which a bipolar transistor of 4-GHz cutoff frequency is combined with standard CMOS devices on the same chip, has been applied to a processor. The design strategy was to provide high integratio
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::7bb6258c53d5ec0a56dff1aa253e535b
https://doi.org/10.1109/jssc.1986.1052611
https://doi.org/10.1109/jssc.1986.1052611
Conference
Tento výsledek nelze pro nepřihlášené uživatele zobrazit.
K zobrazení výsledku je třeba se přihlásit.
K zobrazení výsledku je třeba se přihlásit.
Publikováno v:
Electronics & Communications in Japan, Part 2: Electronics. Sep89, Vol. 72 Issue 9, p1-9. 9p.
Publikováno v:
IEEE Journal of Solid-State Circuits; 1991, Vol. 26 Issue 4, p585-589, 5p
Autor:
Yamashita, T., Yoshida, N., Sakamoto, M., Matsumoto, T., Kusunoki, M., Takahashi, H., Wakahara, A., Ito, T., Shimizu, T., Kurita, K., Higeta, K., Mori, K., Tamba, N., Kato, N., Miyamoto, K., Yamagata, R., Tanaka, H., Hiyama, T.
Publikováno v:
2000 IEEE International Solid-State Circuits Conference. Digest of Technical Papers (Cat. No.00CH37056); 2000, p414-475, 3p
Publikováno v:
Digest of Technical Papers., 1990 Symposium on VLSI Circuits; 1/ 1/1990, p85-86, 2p