Zobrazeno 1 - 10 of 10 pro vyhledávání: '"Koutaro Sho"'
1
Material and Process Development for KrF Lithography using Tri-level Resist Process
Autor: Seiji Nakagawa, Takaya Matsushita, Kazuhiko Urayama, Eishi Shiobara, Tsuyoshi Shibata, Seiji Kajiwara, Koutaro Sho
Publikováno v: Journal of Photopolymer Science and Technology. 14:469-474
A material and process development for tri-level resist process is carried out in terms of both lithography and RIE processes. The goal is to introduce the tri-level resist process into 0.13μm DRAM fabrication. The film stack of the tri-level resist
Externí odkaz: https://explore.openaire.eu/search/publication?articleId=doi_________::667d4c4bbf881ddf808a1c1a02bcb4be
https://doi.org/10.2494/photopolymer.14.469
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3
Feasibility study of non-topcoat resist for 22nm node devices
Autor: Yukio Nishimura, Motoyuki Shima, Koutaro Sho, Takanori Kawakami, Tomoya Ori, Kazunori Iida, Tsukasa Azuma, Daizo Muto, Katsutoshi Kobayashi, Hirokazu Kato, Shinichi Ito, Yuuki Ishii, Tomoharu Fujiwara
Publikováno v: Advances in Resist Materials and Processing Technology XXVI.
Subsequent to 45 nm node, immersion lithography using topcoat process is approaching its next step for mass production. However, microfabrication using immersion topcoat leads to increase in cost due to increase in process steps. In order to deal wit
Externí odkaz: https://explore.openaire.eu/search/publication?articleId=doi_________::38ec01cf8b3d60b69eabb877c0691707
https://doi.org/10.1117/12.812475
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4
Sub-45nm resist process using stacked-mask process
Autor: Hisataka Hayashi, Tokuhisa Ohiwa, Hirokazu Kato, Shinichi Ito, Keisuke Kikutani, Yuriko Seino, Yasunobu Oonishi, Katsutoshi Kobayashi, Seiro Miyoshi, Koutaro Sho, Junko Abe
Publikováno v: Advances in Resist Materials and Processing Technology XXV.
The stacked-mask process (S-MAP) is a tri-level resist process by lithography and dry etching, which consists of thin resist, spin-on-glass (SOG), and spun-on carbon (SOC). However, as design rules progress below 60nm, two problems arise in the conve
Externí odkaz: https://explore.openaire.eu/search/publication?articleId=doi_________::bc93009a004812ee757bb643f7b120a7
https://doi.org/10.1117/12.771840
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5
Patterning strategy and performance of 1.3NA tool for 32nm node lithography
Autor: Katsura Miyashita, Masaki Satake, Katsuyoshi Kodera, Soichi Inoue, Kazuhiro Takahata, Hideaki Harakawa, Yosuke Kitamura, Hiroharu Fujise, Shoji Mimotogi, Koutaro Sho, Tatsuya Ishida, Tatsuhiko Ema, Kenji Yoshida, Suigen Kyoh, Kazutaka Ishigo, Masafumi Asano, Hideki Kanai, Takuya Kono, Akiko Nomachi
Publikováno v: Optical Microlithography XXI.
We have designed the lithography process for 32nm node logic devices under th e 1.3NA single exposure conditions. The simulation and experimental results indicate that the minimum pitches should be determined as 100nm for line pattern and 120nm for c
Externí odkaz: https://explore.openaire.eu/search/publication?articleId=doi_________::f963acc1eddb32aedb38f145a206a9b3
https://doi.org/10.1117/12.772201
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6
Performance of immersion lithography for 45-nm-node CMOS and ultra-high density SRAM with 0.25um2
Autor: Koutaro Sho, Mikio Katsumata, Taiki Kimura, Shoji Mimotogi, Tatsuhiko Ema, Seiji Nagahara, Fumikatsu Uesawa, Makoto Tominaga, Hiroki Hane, Hiroharu Fujise, Atsushi Ikegami, Masafumi Asano, Hideki Kanai, M. Iwai
Publikováno v: SPIE Proceedings.
Immersion lithography was applied to 45nm node logic and 0.25um 2 ultra-high density SRAM. The predictable enhancement of focus margin and resolution were obtained for all levels which were exposed by immersion tool. In particular, the immersion lith
Externí odkaz: https://explore.openaire.eu/search/publication?articleId=doi_________::024f73f27729ff65e39735aaf462d95a
https://doi.org/10.1117/12.711049
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7
Optical lithography technologies for 45-nm node CMOS
Autor: Tomohiro Sugiyama, Suigen Kyoh, Kohji Hashimoto, Shoji Mimotogi, Hideki Kanai, Maki Miyazaki, Eishi Shiobara, Kazuya Sato, Fumikatsu Uesawa, Kazuhiro Takahata, Koutaro Sho, Hiroki Hane, Hiroharu Fujise, Mikio Katsumata
Publikováno v: Optical Microlithography XVIII.
In 45nm-node CMOS, the k1 value is around 0.35. In the low-k1 lithography, the robust design for lens aberration and process fluctuation such as mask CD error is required for manufacturing. The technologies of robust design for 45nm-node CMOS are pro
Externí odkaz: https://explore.openaire.eu/search/publication?articleId=doi_________::b2dbee629174dc6c5f29b413ad5d0c60
https://doi.org/10.1117/12.600948
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8
Application of reversed pattern transfer process for sub-90-nm technology
Autor: Yoshinobu Ohnishi, Kazuhiko Urayama, Hirokazu Kato, Tsuyoshi Shibata, Koutaro Sho, Junko Abe
Publikováno v: Advances in Resist Technology and Processing XX.
A reversed pattern transfer technique combined with ultra thin resist process is discussed. In the reversed pattern transfer technique, first a resist pattern is formed over an organic under layer, next a Water-Soluble Silicone (WSS) is coated on the
Externí odkaz: https://explore.openaire.eu/search/publication?articleId=doi_________::64689354704dd54269cb94234befd9d1
https://doi.org/10.1117/12.485089
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9
Material and process development of tri-level resist system in KrF and ArF lithography
Autor: Koutaro Sho, Hisataka Hayashi, Tsuyoshi Shibata, Yasuhiko Sato, Seiji Nakagawa, Junko Abe
Publikováno v: SPIE Proceedings.
A material and process development of a tri-level resist system is carried out to introduce the resist system into 130nm and 110nm device fabrication. The tri-level resist system consists of organic films as a bottom layer, spin-on- glass (SOG) as a
Externí odkaz: https://explore.openaire.eu/search/publication?articleId=doi_________::d13f291447f8cf3c82e8004148718c01
https://doi.org/10.1117/12.474278
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10
High-accuracy development monitoring technology
Autor: Shinichi Ito, Katsuya Okumura, Kei Hayasaki, Kenji Kawano, Fumio Komatsu, Koutaro Sho, Shoji Mimotogi
Publikováno v: SPIE Proceedings.
A development monitor system capable of highly accurate control of pattern width has been established. This system is composed of a unique monitor pattern on the process wafer, the 0th order diffraction light measuring unit, and the image analysis an
Externí odkaz: https://explore.openaire.eu/search/publication?articleId=doi_________::f751e4f043af905978229d6b3eee3aff
https://doi.org/10.1117/12.346907
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