Zobrazeno 1 - 10
of 15
pro vyhledávání: '"Kouichi Syoubu"'
Publikováno v:
International Journal of Electronics. 86:1377-1384
In this paper, we propose a digital signal processing type frequency locked loop (DSP-FLL) using a frequency difference detector (FDD). Since the DSP-FLL is controlled by the frequency, the pole of the voltage controlled oscillator vanishes in the ba
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::f6bc526a09f65f3e07dec3e7b0fcb6df
https://doi.org/10.1080/002072199132662
https://doi.org/10.1080/002072199132662
Publikováno v:
Analog Integrated Circuits and Signal Processing. 21:117-126
In this paper, we propose a new speedup method of frequency switching time of the prescaler PLL frequency synthesizer using (N+ {{1}\over {2}}) pulse swallow programmable divider. The (N+{{1}\over {2}}) pulse swallow programmable divider can set half
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::877ef2adba331d53e8fda3b5c2b7f691
https://doi.org/10.1023/a:1008361421654
https://doi.org/10.1023/a:1008361421654
Publikováno v:
International Journal of Electronics. 84:123-130
A new speed-up method of lock up time is proposed for the phase locked loop (PLL) frequency synthesizer in the local oscillation circuit of a radio receiver. Doubling of reference frequency is achieved by using a new (NN+ 1/2) programmable divider wh
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::26675e617eaddabc4f006a3fbb188a42
https://doi.org/10.1080/002072198134887
https://doi.org/10.1080/002072198134887
Publikováno v:
IEEE Transactions on Consumer Electronics. 44:827-832
In this paper, we propose a new phase locked loop (PLL) frequency synthesizer utilizing the multiprogrammable divider which can attain a higher speed lock-up time by increasing the loop gain. The effectiveness of the PLL frequency synthesizer with th
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::837aad4f2c8fe06c34d248f667b693ca
https://doi.org/10.1109/30.713201
https://doi.org/10.1109/30.713201
Publikováno v:
Journal of Circuits, Systems and Computers. :395-405
Recently, the speedup of lock up time is required in the Phase Locked Loop (PLL) frequency synthesizer. The fractional-N method is one of the most important techniques among the speedup methods proposed hitherto. The fractional-N programmable divider
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::af83eaa57bec2a4cb33f4c4dc478ddd7
https://doi.org/10.1142/s0218126697000292
https://doi.org/10.1142/s0218126697000292
Publikováno v:
IEEE Transactions on Consumer Electronics. 43:550-558
We propose two items for the fast frequency settling in the phase locked loop (PLL) frequency synthesizer. One is a PLL frequency synthesizer utilizing a frequency detector method speedup circuit (FDMSC). From the experimental results, it is observed
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::ae4ffe559a3dd4be39eba6751fc7f7f2
https://doi.org/10.1109/30.628676
https://doi.org/10.1109/30.628676
Publikováno v:
Proceedings of APCCAS'96 - Asia Pacific Conference on Circuits and Systems.
Conventionally, the division ratio of the programmable divider in the Phase Locked Loop (PLL) frequency synthesizer is an only integer. Therefore, it has been hoped to realize the fractional-N programmable divider which can divide not only an integer
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::1f2701e1a5805eeaea6166cfee84498d
https://doi.org/10.1109/apcas.1996.569215
https://doi.org/10.1109/apcas.1996.569215
Publikováno v:
ISCAS '98. Proceedings of the 1998 IEEE International Symposium on Circuits and Systems (Cat. No.98CH36187).
The lock-up time of a PLL frequency synthesizer depends on each loop gain. In this paper, we pay attention to the gain of a programmable divider which is one of the important elements of PLL, and propose a new method for improving the gain of program
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_dedup___::7e1b1e9dd0ac68a6a88985dce91759d6
https://doi.org/10.1109/iscas.1998.698903
https://doi.org/10.1109/iscas.1998.698903
Publikováno v:
ISCAS '98. Proceedings of the 1998 IEEE International Symposium on Circuits and Systems (Cat. No.98CH36187).
in this paper, we propose a new dual loop digital signal processing type phase locked loop (Dual loop DSP-PLL) using digital signal processing type frequency locked loop (DSP-FLL) which we propose and the first order TAN type DSP-PLL (TAN-DSP-PLL). I
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::c8ac3a01fbbfcc22782f9bd849fcdbdc
https://doi.org/10.1109/iscas.1998.698877
https://doi.org/10.1109/iscas.1998.698877
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